Embedded System Covalidation with RTOS Model and FPGA

• Item type: Trans(1)
• 公開日: 2008-08-27
• タイトル: Embedded System Covalidation with RTOS Model and FPGA
• タイトル / 言語: en
• タイトル: Embedded System Covalidation with RTOS Model and FPGA
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: System-Level Verification
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Graduate School of Information Science Nagoya University
• 著者所属: Graduate School of Information Science Nagoya University
• 著者所属: Graduate School of Information Science Nagoya University
• 著者所属: Graduate School of Information Science Nagoya University
• 著者所属: Graduate School of Information Science Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University
• 著者名: Seiya, Shibata; Shinya, Honda; Yuko, Hara; Hiroyuki, Tomiyama; Hiroaki, Takada
• 著者名(英): Seiya, Shibata; Shinya, Honda; Yuko, Hara; Hiroyuki, Tomiyama; Hiroaki, Takada
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: This paper presents a software/hardware covalidation environment for embedded systems. Our covalidation environment consists of a simulation model of RTOS which fully supports services of ITRON multiple hardware simulators FPGA and a covalidation backplane. All of the simulators are executed concurrently with communication. The RTOS model can be executed on the host computer natively therefore the software can be simulated much faster than on an instruction set simulator. FPGA can execute the hardware much faster than HDL simulators. With the RTOS model and FPGA both application software and hardware can be validated in a short time. In the experiment with using our covalidation environment we perform covalidation of an MPEG4 decoder system and show the effectiveness of the covalidation environment.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: This paper presents a software/hardware covalidation environment for embedded systems. Our covalidation environment consists of a simulation model of RTOS which fully supports services of ITRON, multiple hardware simulators, FPGA and a covalidation backplane. All of the simulators are executed concurrently with communication. The RTOS model can be executed on the host computer natively, therefore the software can be simulated much faster than on an instruction set simulator. FPGA can execute the hardware much faster than HDL simulators. With the RTOS model and FPGA, both application software and hardware can be validated in a short time. In the experiment, with using our covalidation environment, we perform covalidation of an MPEG4 decoder system and show the effectiveness of the covalidation environment.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 1, p. 126-130, 発行日 2008-08-27
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会