{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00018631","sets":["934:1160:1161"]},"path":["1161"],"owner":"1","recid":"18631","title":["Embedded System Covalidation with RTOS Model and FPGA"],"pubdate":{"attribute_name":"公開日","attribute_value":"2008-08-27"},"_buckets":{"deposit":"9039d523-1a60-4126-8f69-b865a97b3cf2"},"_deposit":{"id":"18631","pid":{"type":"depid","value":"18631","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"Embedded System Covalidation with RTOS Model and FPGA","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Embedded System Covalidation with RTOS Model and FPGA"},{"subitem_title":"Embedded System Covalidation with RTOS Model and FPGA","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"System-Level Verification","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2008-08-27","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science  Nagoya University"},{"subitem_text_value":"Graduate School of Information Science  Nagoya University"},{"subitem_text_value":"Graduate School of Information Science  Nagoya University"},{"subitem_text_value":"Graduate School of Information Science  Nagoya University"},{"subitem_text_value":"Graduate School of Information Science  Nagoya University"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science, Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/18631/files/IPSJ-TSLDM0100012.pdf"},"date":[{"dateType":"Available","dateValue":"2008-08-27"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0100012.pdf","filesize":[{"value":"652.8 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"b8aec96b-1d6f-41e2-a262-77d76aa5c1bb","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2008 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Seiya, Shibata"},{"creatorName":"Shinya, Honda"},{"creatorName":"Yuko, Hara"},{"creatorName":"Hiroyuki, Tomiyama"},{"creatorName":"Hiroaki, Takada"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Seiya, Shibata","creatorNameLang":"en"},{"creatorName":"Shinya, Honda","creatorNameLang":"en"},{"creatorName":"Yuko, Hara","creatorNameLang":"en"},{"creatorName":"Hiroyuki, Tomiyama","creatorNameLang":"en"},{"creatorName":"Hiroaki, Takada","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12394951","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6687","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"This paper presents a software/hardware covalidation environment for embedded systems. Our covalidation environment consists of a simulation model of RTOS which fully supports services of ITRON  multiple hardware simulators  FPGA and a covalidation backplane. All of the simulators are executed concurrently with communication. The RTOS model can be executed on the host computer natively  therefore the software can be simulated much faster than on an instruction set simulator. FPGA can execute the hardware much faster than HDL simulators. With the RTOS model and FPGA  both application software and hardware can be validated in a short time. In the experiment  with using our covalidation environment  we perform covalidation of an MPEG4 decoder system and show the effectiveness of the covalidation environment.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper presents a software/hardware covalidation environment for embedded systems. Our covalidation environment consists of a simulation model of RTOS which fully supports services of ITRON, multiple hardware simulators, FPGA and a covalidation backplane. All of the simulators are executed concurrently with communication. The RTOS model can be executed on the host computer natively, therefore the software can be simulated much faster than on an instruction set simulator. FPGA can execute the hardware much faster than HDL simulators. With the RTOS model and FPGA, both application software and hardware can be validated in a short time. In the experiment, with using our covalidation environment, we perform covalidation of an MPEG4 decoder system and show the effectiveness of the covalidation environment.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"130","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology （TSLDM）"}],"bibliographicPageStart":"126","bibliographicIssueDates":{"bibliographicIssueDate":"2008-08-27","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"1"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"updated":"2025-01-22T22:38:41.898128+00:00","created":"2025-01-18T22:51:18.954489+00:00","id":18631}