@article{oai:ipsj.ixsq.nii.ac.jp:00018631,
 author = {Seiya, Shibata and Shinya, Honda and Yuko, Hara and Hiroyuki, Tomiyama and Hiroaki, Takada and Seiya, Shibata and Shinya, Honda and Yuko, Hara and Hiroyuki, Tomiyama and Hiroaki, Takada},
 journal = {IPSJ Transactions on System LSI Design Methodology （TSLDM）},
 month = {Aug},
 note = {This paper presents a software/hardware covalidation environment for embedded systems. Our covalidation environment consists of a simulation model of RTOS which fully supports services of ITRON  multiple hardware simulators  FPGA and a covalidation backplane. All of the simulators are executed concurrently with communication. The RTOS model can be executed on the host computer natively  therefore the software can be simulated much faster than on an instruction set simulator. FPGA can execute the hardware much faster than HDL simulators. With the RTOS model and FPGA  both application software and hardware can be validated in a short time. In the experiment  with using our covalidation environment  we perform covalidation of an MPEG4 decoder system and show the effectiveness of the covalidation environment., This paper presents a software/hardware covalidation environment for embedded systems. Our covalidation environment consists of a simulation model of RTOS which fully supports services of ITRON, multiple hardware simulators, FPGA and a covalidation backplane. All of the simulators are executed concurrently with communication. The RTOS model can be executed on the host computer natively, therefore the software can be simulated much faster than on an instruction set simulator. FPGA can execute the hardware much faster than HDL simulators. With the RTOS model and FPGA, both application software and hardware can be validated in a short time. In the experiment, with using our covalidation environment, we perform covalidation of an MPEG4 decoder system and show the effectiveness of the covalidation environment.},
 pages = {126--130},
 title = {Embedded System Covalidation with RTOS Model and FPGA},
 volume = {1},
 year = {2008}
}