Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures

• Item type: Trans(1)
• 公開日: 2008-08-27
• タイトル: Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures
• タイトル / 言語: en
• タイトル: Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: Behavioral Synthesis
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: School of Fundamental Science and Engineering Waseda University
• 著者所属: School of Fundamental Science and Engineering Waseda University
• 著者所属: School of Fundamental Science and Engineering Waseda University
• 著者所属: School of Fundamental Science and Engineering Waseda University
• 著者所属: School of Fundamental Science and Engineering Waseda University
• 著者所属(英): en
• 著者所属(英): School of Fundamental Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): School of Fundamental Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): School of Fundamental Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): School of Fundamental Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): School of Fundamental Science and Engineering, Waseda University
• 著者名: Akira, Ohchi; Shunitsu, Kohara; Nozomu, Togawa; Masao, Yanagisawa; Tatsuo, Ohtsuki
• 著者名(英): Akira, Ohchi; Shunitsu, Kohara; Nozomu, Togawa; Masao, Yanagisawa; Tatsuo, Ohtsuki
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: In this paper we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding (2) register allocation (3) register binding and (4) module placement. By feeding back floorplan information from (4) to (1) our method obtains a distributed/shared-register architecture where its scheduling/binding as well as floorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.2% while maintaining the performance of the circuit equal with that using distributed-register architectures.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: In this paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back floorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/binding as well as floorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.2% while maintaining the performance of the circuit equal with that using distributed-register architectures.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 1, p. 78-90, 発行日 2008-08-27
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会