{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00018627","sets":["934:1160:1161"]},"path":["1161"],"owner":"1","recid":"18627","title":["Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures"],"pubdate":{"attribute_name":"公開日","attribute_value":"2008-08-27"},"_buckets":{"deposit":"e38444da-a276-4605-b1cf-066d8ae3ffa7"},"_deposit":{"id":"18627","pid":{"type":"depid","value":"18627","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures"},{"subitem_title":"Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Behavioral Synthesis","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2008-08-27","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"School of Fundamental Science and Engineering  Waseda University"},{"subitem_text_value":"School of Fundamental Science and Engineering  Waseda University"},{"subitem_text_value":"School of Fundamental Science and Engineering  Waseda University"},{"subitem_text_value":"School of Fundamental Science and Engineering  Waseda University"},{"subitem_text_value":"School of Fundamental Science and Engineering  Waseda University"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"School of Fundamental Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"School of Fundamental Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"School of Fundamental Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"School of Fundamental Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"School of Fundamental Science and Engineering, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/18627/files/IPSJ-TSLDM0100008.pdf"},"date":[{"dateType":"Available","dateValue":"2008-08-27"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0100008.pdf","filesize":[{"value":"539.9 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"86eed078-330a-4f77-b537-9c62d77d3ff6","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2008 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Akira, Ohchi"},{"creatorName":"Shunitsu, Kohara"},{"creatorName":"Nozomu, Togawa"},{"creatorName":"Masao, Yanagisawa"},{"creatorName":"Tatsuo, Ohtsuki"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Akira, Ohchi","creatorNameLang":"en"},{"creatorName":"Shunitsu, Kohara","creatorNameLang":"en"},{"creatorName":"Nozomu, Togawa","creatorNameLang":"en"},{"creatorName":"Masao, Yanagisawa","creatorNameLang":"en"},{"creatorName":"Tatsuo, Ohtsuki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12394951","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6687","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"In this paper  we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding  (2) register allocation  (3) register binding  and (4) module placement. By feeding back floorplan information from (4) to (1)  our method obtains a distributed/shared-register architecture where its scheduling/binding as well as floorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.2% while maintaining the performance of the circuit equal with that using distributed-register architectures.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back floorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/binding as well as floorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.2% while maintaining the performance of the circuit equal with that using distributed-register architectures.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"90","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology （TSLDM）"}],"bibliographicPageStart":"78","bibliographicIssueDates":{"bibliographicIssueDate":"2008-08-27","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"1"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:51:18.784818+00:00","updated":"2025-01-22T22:38:32.404626+00:00","id":18627}