@article{oai:ipsj.ixsq.nii.ac.jp:00018627,
 author = {Akira, Ohchi and Shunitsu, Kohara and Nozomu, Togawa and Masao, Yanagisawa and Tatsuo, Ohtsuki and Akira, Ohchi and Shunitsu, Kohara and Nozomu, Togawa and Masao, Yanagisawa and Tatsuo, Ohtsuki},
 journal = {IPSJ Transactions on System LSI Design Methodology （TSLDM）},
 month = {Aug},
 note = {In this paper  we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding  (2) register allocation  (3) register binding  and (4) module placement. By feeding back floorplan information from (4) to (1)  our method obtains a distributed/shared-register architecture where its scheduling/binding as well as floorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.2% while maintaining the performance of the circuit equal with that using distributed-register architectures., In this paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back floorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/binding as well as floorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.2% while maintaining the performance of the circuit equal with that using distributed-register architectures.},
 pages = {78--90},
 title = {Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures},
 volume = {1},
 year = {2008}
}