Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs

• Item type: Trans(1)
• 公開日: 2014-02-14
• タイトル: Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs
• タイトル / 言語: en
• タイトル: Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: [Behavioral Synthesis] high-level synthesis, FPGA, resource sharing, register retiming
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Tokyo Institute of Technology
• 著者所属: Nagoya University／Presently with TOYO Corporation
• 著者所属: Ritsumeikan University
• 著者所属: Nagoya University
• 著者所属: Nagoya University
• 著者所属(英): en
• 著者所属(英): Tokyo Institute of Technology
• 著者所属(英): en
• 著者所属(英): Nagoya University / Presently with TOYO Corporation
• 著者所属(英): en
• 著者所属(英): Ritsumeikan University
• 著者所属(英): en
• 著者所属(英): Nagoya University
• 著者所属(英): en
• 著者所属(英): Nagoya University
• 著者名: YukoHara-Azumi; Toshinobu, Matsuba; Hiroyuki, Tomiyama; Shinya, Honda; Hiroaki, Takada
• 著者名(英): Yuko, Hara-Azumi; Toshinobu, Matsuba; Hiroyuki, Tomiyama; Shinya, Honda; Hiroaki, Takada
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Due to the increasing diversity and complexity of embedded systems, the use of high-level synthesis (HLS) and that of FPGAs have been both becoming prevalent in order to enhance the design productivity. Although a number of works for FPGA-oriented optimizations, particularly about resource binding, have been studied in HLS, the HLS technologies are still immature since most of them overlook some important facts on resource sharing. In this paper, for FPGA-based designs, we quantitatively evaluate effects of several resource sharing approaches in HLS using practically large benchmarks, on various FPGA devices. Through the comprehensive evaluation, the effects on clock frequency, execution time, area, and multiplexer distribution are examined. Several important discussions and findings will be disclosed, which are essential for further advance of the practical HLS technology.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Due to the increasing diversity and complexity of embedded systems, the use of high-level synthesis (HLS) and that of FPGAs have been both becoming prevalent in order to enhance the design productivity. Although a number of works for FPGA-oriented optimizations, particularly about resource binding, have been studied in HLS, the HLS technologies are still immature since most of them overlook some important facts on resource sharing. In this paper, for FPGA-based designs, we quantitatively evaluate effects of several resource sharing approaches in HLS using practically large benchmarks, on various FPGA devices. Through the comprehensive evaluation, the effects on clock frequency, execution time, area, and multiplexer distribution are examined. Several important discussions and findings will be disclosed, which are essential for further advance of the practical HLS technology.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 7, p. 37-45, 発行日 2014-02-14
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会