{"id":98684,"created":"2025-01-18T23:44:53.057669+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00098684","sets":["934:1160:7464"]},"path":["7464"],"owner":"11","recid":"98684","title":["Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-02-14"},"_buckets":{"deposit":"2f5c1542-8708-4b08-baf7-27c20524a312"},"_deposit":{"id":"98684","pid":{"type":"depid","value":"98684","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs"},{"subitem_title":"Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"[Behavioral Synthesis] high-level synthesis, FPGA, resource sharing, register retiming","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2014-02-14","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Tokyo Institute of Technology"},{"subitem_text_value":"Nagoya University／Presently with TOYO Corporation"},{"subitem_text_value":"Ritsumeikan University"},{"subitem_text_value":"Nagoya University"},{"subitem_text_value":"Nagoya University"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Nagoya University / Presently with TOYO Corporation","subitem_text_language":"en"},{"subitem_text_value":"Ritsumeikan University","subitem_text_language":"en"},{"subitem_text_value":"Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"Nagoya University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/98684/files/IPSJ-TSLDM0700005.pdf"},"date":[{"dateType":"Available","dateValue":"2014-02-14"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0700005.pdf","filesize":[{"value":"1.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"e35f1a2d-bc51-4ba3-998a-fb51680954e1","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"YukoHara-Azumi"},{"creatorName":"Toshinobu, Matsuba"},{"creatorName":"Hiroyuki, Tomiyama"},{"creatorName":"Shinya, Honda"},{"creatorName":"Hiroaki, Takada"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuko, Hara-Azumi","creatorNameLang":"en"},{"creatorName":"Toshinobu, Matsuba","creatorNameLang":"en"},{"creatorName":"Hiroyuki, Tomiyama","creatorNameLang":"en"},{"creatorName":"Shinya, Honda","creatorNameLang":"en"},{"creatorName":"Hiroaki, Takada","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12394951","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6687","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Due to the increasing diversity and complexity of embedded systems, the use of high-level synthesis (HLS) and that of FPGAs have been both becoming prevalent in order to enhance the design productivity. Although a number of works for FPGA-oriented optimizations, particularly about resource binding, have been studied in HLS, the HLS technologies are still immature since most of them overlook some important facts on resource sharing. In this paper, for FPGA-based designs, we quantitatively evaluate effects of several resource sharing approaches in HLS using practically large benchmarks, on various FPGA devices. Through the comprehensive evaluation, the effects on clock frequency, execution time, area, and multiplexer distribution are examined. Several important discussions and findings will be disclosed, which are essential for further advance of the practical HLS technology.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Due to the increasing diversity and complexity of embedded systems, the use of high-level synthesis (HLS) and that of FPGAs have been both becoming prevalent in order to enhance the design productivity. Although a number of works for FPGA-oriented optimizations, particularly about resource binding, have been studied in HLS, the HLS technologies are still immature since most of them overlook some important facts on resource sharing. In this paper, for FPGA-based designs, we quantitatively evaluate effects of several resource sharing approaches in HLS using practically large benchmarks, on various FPGA devices. Through the comprehensive evaluation, the effects on clock frequency, execution time, area, and multiplexer distribution are examined. Several important discussions and findings will be disclosed, which are essential for further advance of the practical HLS technology.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"45","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology （TSLDM）"}],"bibliographicPageStart":"37","bibliographicIssueDates":{"bibliographicIssueDate":"2014-02-14","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"7"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"links":{},"updated":"2025-01-21T12:21:50.928531+00:00"}