A Method of Software Development Tool and Hardware Generation for ASIP with a Co-processor based on the Derivative ASIP Approach

• Item type: Journal(1)
• 公開日: 2014-02-15
• タイトル: A Method of Software Development Tool and Hardware Generation for ASIP with a Co-processor based on the Derivative ASIP Approach
• タイトル / 言語: en
• タイトル: A Method of Software Development Tool and Hardware Generation for ASIP with a Co-processor based on the Derivative ASIP Approach
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: [特集：組込みシステム工学] ASIP, LISA, GCC Compiler, ImpulseC, instruction extension.
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Kunieda-Isshiki Laboratory, Department of Communications and Computer Engineering, Tokyo Institute of Technology
• 著者所属: Kunieda-Isshiki Laboratory, Department of Communications and Computer Engineering, Tokyo Institute of Technology
• 著者所属: Kunieda-Isshiki Laboratory, Department of Communications and Computer Engineering, Tokyo Institute of Technology
• 著者所属: Kunieda-Isshiki Laboratory, Department of Communications and Computer Engineering, Tokyo Institute of Technology
• 著者所属(英): en
• 著者所属(英): Kunieda-Isshiki Laboratory, Department of Communications and Computer Engineering, Tokyo Institute of Technology
• 著者所属(英): en
• 著者所属(英): Kunieda-Isshiki Laboratory, Department of Communications and Computer Engineering, Tokyo Institute of Technology
• 著者所属(英): en
• 著者所属(英): Kunieda-Isshiki Laboratory, Department of Communications and Computer Engineering, Tokyo Institute of Technology
• 著者所属(英): en
• 著者所属(英): Kunieda-Isshiki Laboratory, Department of Communications and Computer Engineering, Tokyo Institute of Technology
• 著者名: Agus, Bejo; Dongju, Li; Tsuyoshi, Isshiki; Hiroaki, Kunieda
• 著者名(英): Agus, Bejo; Dongju, Li; Tsuyoshi, Isshiki; Hiroaki, Kunieda
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: In this paper, a processor design method using the Derivative ASIP approach is introduced. The concept of Derivative ASIP is basically to develop an ASIP architecture based on existing GPP processor architecture in order to diminish the design effort and shorten the design time. In this approach, the base processor architecture can be enhanced with more co-processor/instruction extensions quickly since all the required development tools have been available for the base processor. In order to support the Derivative ASIP approach, a new tool called the Co-processor/Instruction Extension Generator Tool is developed. This tool generates complementary files suitable for updating the base processor architecture with co-processor/instruction extensions. A complete set of software development tools consisting of a compiler, assembler, disassembler, linker, debugger, simulator and also hardware implementation for the modified ASIP architecture can be generated automatically by using these complementary files. With our proposed tool, a new co-processor/instruction extension can be designed and added to the base architecture more easily. It contributes to the reduction of the architecture exploration time in the design stage. Derivative ARM ASIP architecture enhanced with instruction extensions for the AES algorithm and a co-processor for the fingerprint navigation algorithm is given to demonstrate the effectiveness of our approach.; ------------------------------; This is a preprint of an article intended for publication Journal of; Information Processing(JIP). This preprint should not be cited. This; article should be cited as: Journal of Information Processing Vol.22(2014) No.2 (online); DOI http://dx.doi.org/10.2197/ipsjjip.22.131; ------------------------------
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: In this paper, a processor design method using the Derivative ASIP approach is introduced. The concept of Derivative ASIP is basically to develop an ASIP architecture based on existing GPP processor architecture in order to diminish the design effort and shorten the design time. In this approach, the base processor architecture can be enhanced with more co-processor/instruction extensions quickly since all the required development tools have been available for the base processor. In order to support the Derivative ASIP approach, a new tool called the Co-processor/Instruction Extension Generator Tool is developed. This tool generates complementary files suitable for updating the base processor architecture with co-processor/instruction extensions. A complete set of software development tools consisting of a compiler, assembler, disassembler, linker, debugger, simulator and also hardware implementation for the modified ASIP architecture can be generated automatically by using these complementary files. With our proposed tool, a new co-processor/instruction extension can be designed and added to the base architecture more easily. It contributes to the reduction of the architecture exploration time in the design stage. Derivative ARM ASIP architecture enhanced with instruction extensions for the AES algorithm and a co-processor for the fingerprint navigation algorithm is given to demonstrate the effectiveness of our approach.; ------------------------------; This is a preprint of an article intended for publication Journal of; Information Processing(JIP). This preprint should not be cited. This; article should be cited as: Journal of Information Processing Vol.22(2014) No.2 (online); DOI http://dx.doi.org/10.2197/ipsjjip.22.131; ------------------------------
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN00116647
• 書誌情報: 情報処理学会論文誌; 巻 55, 号 2, 発行日 2014-02-15
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-7764