{"created":"2025-01-18T23:44:45.202130+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00098522","sets":["581:7397:7450"]},"path":["7450"],"owner":"11","recid":"98522","title":["A Method of Software Development Tool and Hardware Generation for ASIP with a Co-processor based on the Derivative ASIP Approach"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-02-15"},"_buckets":{"deposit":"2ca96b2e-6a0b-43de-a1a3-0199c2789a17"},"_deposit":{"id":"98522","pid":{"type":"depid","value":"98522","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"A Method of Software Development Tool and Hardware Generation for ASIP with a Co-processor based on the Derivative ASIP Approach","author_link":["358730","358733","358734","358729","358727","358732","358728","358731"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"A Method of Software Development Tool and Hardware Generation for ASIP with a Co-processor based on the Derivative ASIP Approach"},{"subitem_title":"A Method of Software Development Tool and Hardware Generation for ASIP with a Co-processor based on the Derivative ASIP Approach","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"[特集：組込みシステム工学] ASIP, LISA, GCC Compiler, ImpulseC, instruction extension.","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"2014-02-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Kunieda-Isshiki Laboratory, Department of Communications and Computer Engineering, Tokyo Institute of Technology"},{"subitem_text_value":"Kunieda-Isshiki Laboratory, Department of Communications and Computer Engineering, Tokyo Institute of Technology"},{"subitem_text_value":"Kunieda-Isshiki Laboratory, Department of Communications and Computer Engineering, Tokyo Institute of Technology"},{"subitem_text_value":"Kunieda-Isshiki Laboratory, Department of Communications and Computer Engineering, Tokyo Institute of Technology"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Kunieda-Isshiki Laboratory, Department of Communications and Computer Engineering, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Kunieda-Isshiki Laboratory, Department of Communications and Computer Engineering, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Kunieda-Isshiki Laboratory, Department of Communications and Computer Engineering, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Kunieda-Isshiki Laboratory, Department of Communications and Computer Engineering, Tokyo Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"publish_status":"0","weko_shared_id":11,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/98522/files/IPSJ-JNL5502046.pdf","label":"IPSJ-JNL5502046"},"date":[{"dateType":"Available","dateValue":"2016-02-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL5502046.pdf","filesize":[{"value":"3.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"7d273323-38a2-44c4-9cff-eaa27969d68f","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Agus, Bejo"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Dongju, Li"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tsuyoshi, Isshiki"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroaki, Kunieda"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Agus, Bejo","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Dongju, Li","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tsuyoshi, Isshiki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroaki, Kunieda","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"In this paper, a processor design method using the Derivative ASIP approach is introduced. The concept of Derivative ASIP is basically to develop an ASIP architecture based on existing GPP processor architecture in order to diminish the design effort and shorten the design time. In this approach, the base processor architecture can be enhanced with more co-processor/instruction extensions quickly since all the required development tools have been available for the base processor. In order to support the Derivative ASIP approach, a new tool called the Co-processor/Instruction Extension Generator Tool is developed. This tool generates complementary files suitable for updating the base processor architecture with co-processor/instruction extensions. A complete set of software development tools consisting of a compiler, assembler, disassembler, linker, debugger, simulator and also hardware implementation for the modified ASIP architecture can be generated automatically by using these complementary files. With our proposed tool, a new co-processor/instruction extension can be designed and added to the base architecture more easily. It contributes to the reduction of the architecture exploration time in the design stage. Derivative ARM ASIP architecture enhanced with instruction extensions for the AES algorithm and a co-processor for the fingerprint navigation algorithm is given to demonstrate the effectiveness of our approach.\n\n------------------------------\nThis is a preprint of an article intended for publication Journal of\nInformation Processing(JIP). This preprint should not be cited. This\narticle should be cited as: Journal of Information Processing Vol.22(2014) No.2 (online)\nDOI http://dx.doi.org/10.2197/ipsjjip.22.131\n------------------------------","subitem_description_type":"Other"}]},"item_2_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this paper, a processor design method using the Derivative ASIP approach is introduced. The concept of Derivative ASIP is basically to develop an ASIP architecture based on existing GPP processor architecture in order to diminish the design effort and shorten the design time. In this approach, the base processor architecture can be enhanced with more co-processor/instruction extensions quickly since all the required development tools have been available for the base processor. In order to support the Derivative ASIP approach, a new tool called the Co-processor/Instruction Extension Generator Tool is developed. This tool generates complementary files suitable for updating the base processor architecture with co-processor/instruction extensions. A complete set of software development tools consisting of a compiler, assembler, disassembler, linker, debugger, simulator and also hardware implementation for the modified ASIP architecture can be generated automatically by using these complementary files. With our proposed tool, a new co-processor/instruction extension can be designed and added to the base architecture more easily. It contributes to the reduction of the architecture exploration time in the design stage. Derivative ARM ASIP architecture enhanced with instruction extensions for the AES algorithm and a co-processor for the fingerprint navigation algorithm is given to demonstrate the effectiveness of our approach.\n\n------------------------------\nThis is a preprint of an article intended for publication Journal of\nInformation Processing(JIP). This preprint should not be cited. This\narticle should be cited as: Journal of Information Processing Vol.22(2014) No.2 (online)\nDOI http://dx.doi.org/10.2197/ipsjjip.22.131\n------------------------------","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicIssueDates":{"bibliographicIssueDate":"2014-02-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2","bibliographicVolumeNumber":"55"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":98522,"updated":"2025-01-20T06:47:08.045168+00:00","links":{}}