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  1. 論文誌(トランザクション)
  2. System LSI Design Methodology(TSLDM)
  3. Vol.6

Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks

https://ipsj.ixsq.nii.ac.jp/records/94819
https://ipsj.ixsq.nii.ac.jp/records/94819
875b7ff4-49ec-4d69-acb6-141fc5fd6fa1
名前 / ファイル ライセンス アクション
IPSJ-TSLDM0600015.pdf IPSJ-TSLDM0600015.pdf (856.3 kB)
Copyright (c) 2013 by the Information Processing Society of Japan
オープンアクセス
Item type Trans(1)
公開日 2013-08-05
タイトル
タイトル Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks
タイトル
言語 en
タイトル Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks
言語
言語 eng
キーワード
主題Scheme Other
主題 [Behavioral Synthesis] high-level synthesis, multiplexer, resource sharing
資源タイプ
資源タイプ識別子 http://purl.org/coar/resource_type/c_6501
資源タイプ journal article
著者所属
Nara Institute of Science and Technology
著者所属
Nagoya University/Presently with TOYO Corporation
著者所属
Ritsumeikan University
著者所属
Nagoya University
著者所属
Nagoya University
著者所属(英)
en
Nara Institute of Science and Technology
著者所属(英)
en
Nagoya University / Presently with TOYO Corporation
著者所属(英)
en
Ritsumeikan University
著者所属(英)
en
Nagoya University
著者所属(英)
en
Nagoya University
著者名 YukoHara-Azumi Toshinobu, Matsuba Hiroyuki, Tomiyama Shinya, Honda Hiroaki, Takada

× YukoHara-Azumi Toshinobu, Matsuba Hiroyuki, Tomiyama Shinya, Honda Hiroaki, Takada

YukoHara-Azumi
Toshinobu, Matsuba
Hiroyuki, Tomiyama
Shinya, Honda
Hiroaki, Takada

Search repository
著者名(英) Yuko, Hara-Azumi Toshinobu, Matsuba Hiroyuki, Tomiyama Shinya, Honda Hiroaki, Takada

× Yuko, Hara-Azumi Toshinobu, Matsuba Hiroyuki, Tomiyama Shinya, Honda Hiroaki, Takada

en Yuko, Hara-Azumi
Toshinobu, Matsuba
Hiroyuki, Tomiyama
Shinya, Honda
Hiroaki, Takada

Search repository
論文抄録
内容記述タイプ Other
内容記述 For FPGA-based designs generated through high-level synthesis (HLS), effects of resource sharing/unsharing on clock frequency, execution time, and area are quantitatively evaluated for several practically large benchmarks on multiple FPGA devices. Through experiments, we observed five important findings about resource sharing/unsharing, which are contrary to conventional wisdom or have not been sufficiently handled. These five findings will be useful for the further development and advance of the practical HLS technology.
論文抄録(英)
内容記述タイプ Other
内容記述 For FPGA-based designs generated through high-level synthesis (HLS), effects of resource sharing/unsharing on clock frequency, execution time, and area are quantitatively evaluated for several practically large benchmarks on multiple FPGA devices. Through experiments, we observed five important findings about resource sharing/unsharing, which are contrary to conventional wisdom or have not been sufficiently handled. These five findings will be useful for the further development and advance of the practical HLS technology.
書誌レコードID
収録物識別子タイプ NCID
収録物識別子 AA12394951
書誌情報 IPSJ Transactions on System LSI Design Methodology (TSLDM)

巻 6, p. 122-126, 発行日 2013-08-05
ISSN
収録物識別子タイプ ISSN
収録物識別子 1882-6687
出版者
言語 ja
出版者 情報処理学会
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