@article{oai:ipsj.ixsq.nii.ac.jp:00094819,
 author = {YukoHara-Azumi and Toshinobu, Matsuba and Hiroyuki, Tomiyama and Shinya, Honda and Hiroaki, Takada and Yuko, Hara-Azumi and Toshinobu, Matsuba and Hiroyuki, Tomiyama and Shinya, Honda and Hiroaki, Takada},
 journal = {IPSJ Transactions on System LSI Design Methodology （TSLDM）},
 month = {Aug},
 note = {For FPGA-based designs generated through high-level synthesis (HLS), effects of resource sharing/unsharing on clock frequency, execution time, and area are quantitatively evaluated for several practically large benchmarks on multiple FPGA devices. Through experiments, we observed five important findings about resource sharing/unsharing, which are contrary to conventional wisdom or have not been sufficiently handled. These five findings will be useful for the further development and advance of the practical HLS technology., For FPGA-based designs generated through high-level synthesis (HLS), effects of resource sharing/unsharing on clock frequency, execution time, and area are quantitatively evaluated for several practically large benchmarks on multiple FPGA devices. Through experiments, we observed five important findings about resource sharing/unsharing, which are contrary to conventional wisdom or have not been sufficiently handled. These five findings will be useful for the further development and advance of the practical HLS technology.},
 pages = {122--126},
 title = {Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks},
 volume = {6},
 year = {2013}
}