A Fast Performance Estimation Framework for System-Level Design Space Exploration

• Item type: Trans(1)
• 公開日: 2012-02-21
• タイトル: A Fast Performance Estimation Framework for System-Level Design Space Exploration
• タイトル / 言語: en
• タイトル: A Fast Performance Estimation Framework for System-Level Design Space Exploration
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: System-Level Performance Analysis
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Graduate School of Information Science, Nagoya University／Japan Society for the Promotion of Science
• 著者所属: Graduate School of Information Science, Nagoya University
• 著者所属: Graduate School of Information Science, Nagoya University
• 著者所属: College of Science and Engineering, Ritsumeikan University
• 著者所属: Graduate School of Information Science, Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University / Japan Society for the Promotion of Science
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University
• 著者所属(英): en
• 著者所属(英): College of Science and Engineering, Ritsumeikan University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University
• 著者名: Seiya, Shibata; Yuki, Ando; Shinya, Honda; Hiroyuki, Tomiyama; Hiroaki, Takada
• 著者名(英): Seiya, Shibata; Yuki, Ando; Shinya, Honda; Hiroyuki, Tomiyama; Hiroaki, Takada
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: This paper presents a fast performance estimation framework and an performance estimation method for design space exploration at system level. As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. In order to shorten the evaluation time, we have developed a fast design space exploration framework which combines our system-level design tool, named SystemBuilder, and a newly developed fast performance estimation tool, named SystemPerfEst. SystemPerfEst is based on trace-based simulation method. The trace is obtained as the result of SystemBuilder, and the trace is fed to SystemPerfEst smoothly. Since the estimation of a design candidate finishes in about one second, design space exploration of a number of design candidates can be performed with SystemPerfEst in a practical time. A case study on design space exploration of a JPEG decoder system demonstrates the effectiveness of our framework.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: This paper presents a fast performance estimation framework and an performance estimation method for design space exploration at system level. As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. In order to shorten the evaluation time, we have developed a fast design space exploration framework which combines our system-level design tool, named SystemBuilder, and a newly developed fast performance estimation tool, named SystemPerfEst. SystemPerfEst is based on trace-based simulation method. The trace is obtained as the result of SystemBuilder, and the trace is fed to SystemPerfEst smoothly. Since the estimation of a design candidate finishes in about one second, design space exploration of a number of design candidates can be performed with SystemPerfEst in a practical time. A case study on design space exploration of a JPEG decoder system demonstrates the effectiveness of our framework.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology（TSLDM）; 巻 5, p. 44-54, 発行日 2012-02-21
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会