{"links":{},"id":81498,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00081498","sets":["934:1160:6745"]},"path":["6745"],"owner":"11","recid":"81498","title":["A Fast Performance Estimation Framework for System-Level Design Space Exploration"],"pubdate":{"attribute_name":"公開日","attribute_value":"2012-02-21"},"_buckets":{"deposit":"50e9b994-1b26-4e60-8bfa-a6647707c937"},"_deposit":{"id":"81498","pid":{"type":"depid","value":"81498","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"A Fast Performance Estimation Framework for System-Level Design Space Exploration","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"A Fast Performance Estimation Framework for System-Level Design Space Exploration"},{"subitem_title":"A Fast Performance Estimation Framework for System-Level Design Space Exploration","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"System-Level Performance Analysis","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2012-02-21","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science, Nagoya University／Japan Society for the Promotion of Science"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University"},{"subitem_text_value":"College of Science and Engineering, Ritsumeikan University"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science, Nagoya University / Japan Society for the Promotion of Science","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"College of Science and Engineering, Ritsumeikan University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/81498/files/IPSJ-TSLDM0500006.pdf"},"date":[{"dateType":"Available","dateValue":"2014-02-21"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0500006.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"31246f5f-7df6-4aa8-a9de-2b6288f739db","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2012 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Seiya, Shibata"},{"creatorName":"Yuki, Ando"},{"creatorName":"Shinya, Honda"},{"creatorName":"Hiroyuki, Tomiyama"},{"creatorName":"Hiroaki, Takada"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Seiya, Shibata","creatorNameLang":"en"},{"creatorName":"Yuki, Ando","creatorNameLang":"en"},{"creatorName":"Shinya, Honda","creatorNameLang":"en"},{"creatorName":"Hiroyuki, Tomiyama","creatorNameLang":"en"},{"creatorName":"Hiroaki, Takada","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12394951","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6687","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"This paper presents a fast performance estimation framework and an performance estimation method for design space exploration at system level. As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. In order to shorten the evaluation time, we have developed a fast design space exploration framework which combines our system-level design tool, named SystemBuilder, and a newly developed fast performance estimation tool, named SystemPerfEst. SystemPerfEst is based on trace-based simulation method. The trace is obtained as the result of SystemBuilder, and the trace is fed to SystemPerfEst smoothly. Since the estimation of a design candidate finishes in about one second, design space exploration of a number of design candidates can be performed with SystemPerfEst in a practical time. A case study on design space exploration of a JPEG decoder system demonstrates the effectiveness of our framework.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper presents a fast performance estimation framework and an performance estimation method for design space exploration at system level. As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. In order to shorten the evaluation time, we have developed a fast design space exploration framework which combines our system-level design tool, named SystemBuilder, and a newly developed fast performance estimation tool, named SystemPerfEst. SystemPerfEst is based on trace-based simulation method. The trace is obtained as the result of SystemBuilder, and the trace is fed to SystemPerfEst smoothly. Since the estimation of a design candidate finishes in about one second, design space exploration of a number of design candidates can be performed with SystemPerfEst in a practical time. A case study on design space exploration of a JPEG decoder system demonstrates the effectiveness of our framework.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"54","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology（TSLDM）"}],"bibliographicPageStart":"44","bibliographicIssueDates":{"bibliographicIssueDate":"2012-02-21","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"5"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:35:40.464928+00:00","updated":"2025-01-21T19:20:35.395863+00:00"}