Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation

• Item type: Trans(1)
• 公開日: 2010-08-16
• タイトル: Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation
• タイトル / 言語: en
• タイトル: Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: System-Level Performance Analysis
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Graduate School of Information Science, Nagoya University / Japan Society for the Promotion of Science
• 著者所属: Graduate School of Information Science, Nagoya University
• 著者所属: Graduate School of Information Science, Nagoya University
• 著者所属: College of Science and Engineering, Ritsumeikan University
• 著者所属: Graduate School of Information Science, Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University / Japan Society for the Promotion of Science
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University
• 著者所属(英): en
• 著者所属(英): College of Science and Engineering, Ritsumeikan University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University
• 著者名: Seiya, Shibata; Yuki, Ando; Shinya, Honda; Hiroyuki, Tomiyama; Hiroaki, Takada
• 著者名(英): Seiya, Shibata; Yuki, Ando; Shinya, Honda; Hiroyuki, Tomiyama; Hiroaki, Takada
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. We have developed two profilers, a process profiler and a memory profiler, for FPGA-based performance analysis of design candidates. The process profiler records a trace of process activations, while the memory profiler records a trace of channel accesses. According to mapping of processes to PEs, the profilers are automatically configured and instrumented into FPGA-based system prototypes by a system-level design tool that we have developed. Designers therefore need to manually modify neither the system description nor the profilers upon each change of process mapping. In order to demonstrate the effectiveness of our profilers, two case studies are conducted where the profiles are used for design space exploration of AES encryption and MPEG4 decoding systems.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. We have developed two profilers, a process profiler and a memory profiler, for FPGA-based performance analysis of design candidates. The process profiler records a trace of process activations, while the memory profiler records a trace of channel accesses. According to mapping of processes to PEs, the profilers are automatically configured and instrumented into FPGA-based system prototypes by a system-level design tool that we have developed. Designers therefore need to manually modify neither the system description nor the profilers upon each change of process mapping. In order to demonstrate the effectiveness of our profilers, two case studies are conducted where the profiles are used for design space exploration of AES encryption and MPEG4 decoding systems.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology（TSLDM）; 巻 3, p. 179-193, 発行日 2010-08-16
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会