{"id":70254,"created":"2025-01-18T23:29:31.645566+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00070254","sets":["934:1160:6049"]},"path":["6049"],"owner":"10","recid":"70254","title":["Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation"],"pubdate":{"attribute_name":"公開日","attribute_value":"2010-08-16"},"_buckets":{"deposit":"8774f81e-097c-4590-b063-51d06bc4d763"},"_deposit":{"id":"70254","pid":{"type":"depid","value":"70254","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation"},{"subitem_title":"Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"System-Level Performance Analysis","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2010-08-16","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science, Nagoya University / Japan Society for the Promotion of Science"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University"},{"subitem_text_value":"College of Science and Engineering, Ritsumeikan University"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science, Nagoya University / Japan Society for the Promotion of Science","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"College of Science and Engineering, Ritsumeikan University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Nagoya University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":10,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/70254/files/IPSJ-TSLDM0300015.pdf","label":"IPSJ-TSLDM0300015"},"date":[{"dateType":"Available","dateValue":"2012-08-16"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0300015.pdf","filesize":[{"value":"1.6 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"da242b87-bb96-48de-a9c5-f31ea62772c8","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2010 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Seiya, Shibata"},{"creatorName":"Yuki, Ando"},{"creatorName":"Shinya, Honda"},{"creatorName":"Hiroyuki, Tomiyama"},{"creatorName":"Hiroaki, Takada"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Seiya, Shibata","creatorNameLang":"en"},{"creatorName":"Yuki, Ando","creatorNameLang":"en"},{"creatorName":"Shinya, Honda","creatorNameLang":"en"},{"creatorName":"Hiroyuki, Tomiyama","creatorNameLang":"en"},{"creatorName":"Hiroaki, Takada","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12394951","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6687","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. We have developed two profilers, a process profiler and a memory profiler, for FPGA-based performance analysis of design candidates. The process profiler records a trace of process activations, while the memory profiler records a trace of channel accesses. According to mapping of processes to PEs, the profilers are automatically configured and instrumented into FPGA-based system prototypes by a system-level design tool that we have developed. Designers therefore need to manually modify neither the system description nor the profilers upon each change of process mapping. In order to demonstrate the effectiveness of our profilers, two case studies are conducted where the profiles are used for design space exploration of AES encryption and MPEG4 decoding systems.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. We have developed two profilers, a process profiler and a memory profiler, for FPGA-based performance analysis of design candidates. The process profiler records a trace of process activations, while the memory profiler records a trace of channel accesses. According to mapping of processes to PEs, the profilers are automatically configured and instrumented into FPGA-based system prototypes by a system-level design tool that we have developed. Designers therefore need to manually modify neither the system description nor the profilers upon each change of process mapping. In order to demonstrate the effectiveness of our profilers, two case studies are conducted where the profiles are used for design space exploration of AES encryption and MPEG4 decoding systems.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"193","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology（TSLDM）"}],"bibliographicPageStart":"179","bibliographicIssueDates":{"bibliographicIssueDate":"2010-08-16","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"3"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"updated":"2025-01-21T22:38:29.558216+00:00","links":{}}