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A Generalized Framework for Energy Savings in Hard Real-Time Embedded Systems
https://ipsj.ixsq.nii.ac.jp/records/66212
https://ipsj.ixsq.nii.ac.jp/records/66212eeb6922b-8904-427b-b18b-fd21338c07de
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
IPSJ-TSLDM0200016.pdf (611.7 kB)
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Copyright (c) 2009 by the Information Processing Society of Japan
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| オープンアクセス | ||
| Item type | Trans(1) | |||||||
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| 公開日 | 2009-08-14 | |||||||
| タイトル | ||||||||
| タイトル | A Generalized Framework for Energy Savings in Hard Real-Time Embedded Systems | |||||||
| タイトル | ||||||||
| 言語 | en | |||||||
| タイトル | A Generalized Framework for Energy Savings in Hard Real-Time Embedded Systems | |||||||
| 言語 | ||||||||
| 言語 | eng | |||||||
| キーワード | ||||||||
| 主題Scheme | Other | |||||||
| 主題 | System-Level Low-Power Design | |||||||
| 資源タイプ | ||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||
| 資源タイプ | journal article | |||||||
| 著者所属 | ||||||||
| Graduate School of Information Science, Nagoya University | ||||||||
| 著者所属 | ||||||||
| Graduate School of Information Science, Nagoya University | ||||||||
| 著者所属 | ||||||||
| Graduate School of Information Science, Nagoya University | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Graduate School of Information Science, Nagoya University | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Graduate School of Information Science, Nagoya University | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Graduate School of Information Science, Nagoya University | ||||||||
| 著者名 |
Gang, Zeng
Hiroyuki, Tomiyama
Hiroaki, Takada
× Gang, Zeng Hiroyuki, Tomiyama Hiroaki, Takada
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| 著者名(英) |
Gang, Zeng
Hiroyuki, Tomiyama
Hiroaki, Takada
× Gang, Zeng Hiroyuki, Tomiyama Hiroaki, Takada
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| 論文抄録 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | A dynamic energy performance scaling (DEPS) framework is proposed for energy savings in hard real-time embedded systems. In this generalized framework, two existing technologies, i.e., dynamic hardware resource configuration (DHRC) and dynamic voltage frequency scaling (DVFS) are combined for energy performance tradeoff. The problem of selecting the optimal hardware configuration and voltage/frequency parameters is formulated to achieve maximal energy savings and meet the deadline constraint simultaneously. Through case studies, the effectiveness of DEPS has been validated. | |||||||
| 論文抄録(英) | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | A dynamic energy performance scaling (DEPS) framework is proposed for energy savings in hard real-time embedded systems. In this generalized framework, two existing technologies, i.e., dynamic hardware resource configuration (DHRC) and dynamic voltage frequency scaling (DVFS) are combined for energy performance tradeoff. The problem of selecting the optimal hardware configuration and voltage/frequency parameters is formulated to achieve maximal energy savings and meet the deadline constraint simultaneously. Through case studies, the effectiveness of DEPS has been validated. | |||||||
| 書誌レコードID | ||||||||
| 収録物識別子タイプ | NCID | |||||||
| 収録物識別子 | AA12394951 | |||||||
| 書誌情報 |
IPSJ Transactions on System LSI Design Methodology （TSLDM） 巻 2, p. 167-179, 発行日 2009-08-14 |
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| ISSN | ||||||||
| 収録物識別子タイプ | ISSN | |||||||
| 収録物識別子 | 1882-6687 | |||||||
| 出版者 | ||||||||
| 言語 | ja | |||||||
| 出版者 | 情報処理学会 | |||||||
