| Item type |
SIG Technical Reports(1) |
| 公開日 |
2021-03-22 |
| タイトル |
|
|
タイトル |
Optimization of Quantum Computing Simulation with Gate Fusion |
| タイトル |
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言語 |
en |
|
タイトル |
Optimization of Quantum Computing Simulation with Gate Fusion |
| 言語 |
|
|
言語 |
eng |
| 資源タイプ |
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|
資源タイプ識別子 |
http://purl.org/coar/resource_type/c_18gh |
|
資源タイプ |
technical report |
| 著者所属 |
|
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|
IBM Quantum, IBM Research Tokyo |
| 著者所属 |
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IBM Quantum, IBM Research Tokyo |
| 著者所属(英) |
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en |
|
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IBM Quantum, IBM Research Tokyo |
| 著者所属(英) |
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en |
|
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IBM Quantum, IBM Research Tokyo |
| 著者名 |
Hiroshi, Horii
Jun, Doi
|
| 著者名(英) |
Hiroshi, Horii
Jun, Doi
|
| 論文抄録 |
|
|
内容記述タイプ |
Other |
|
内容記述 |
Memory to simulate quantum computing is exponentially increased based on qubits of a circuit and the entire memory is updated for simulation of each gate in a circuit to be simulated. For example, 32 GB memory is necessary to represent all the probability amplitudes with double-precision and all of them is updated for each gate. Aggregating multiple gates into a single unitary-matrix gate reduces load and store of memory. However, if an aggregated gate updates many qubits, memory access and calculation of intermediate state of matrix multiplication can become the bottleneck. We propose a method to efficiently aggregate gates with pattern-matchings, greedy algorithms, and a graph algorithm. Our gate fusion reduced gates of various quantum circuits of Qiskit and improved performance of their simulation. |
| 論文抄録(英) |
|
|
内容記述タイプ |
Other |
|
内容記述 |
Memory to simulate quantum computing is exponentially increased based on qubits of a circuit and the entire memory is updated for simulation of each gate in a circuit to be simulated. For example, 32 GB memory is necessary to represent all the probability amplitudes with double-precision and all of them is updated for each gate. Aggregating multiple gates into a single unitary-matrix gate reduces load and store of memory. However, if an aggregated gate updates many qubits, memory access and calculation of intermediate state of matrix multiplication can become the bottleneck. We propose a method to efficiently aggregate gates with pattern-matchings, greedy algorithms, and a graph algorithm. Our gate fusion reduced gates of various quantum circuits of Qiskit and improved performance of their simulation. |
| 書誌レコードID |
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収録物識別子タイプ |
NCID |
|
収録物識別子 |
AA12894105 |
| 書誌情報 |
研究報告量子ソフトウェア（QS）
巻 2021-QS-2,
号 23,
p. 1-7,
発行日 2021-03-22
|
| ISSN |
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収録物識別子タイプ |
ISSN |
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収録物識別子 |
2435-6492 |
| Notice |
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SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc. |
| 出版者 |
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言語 |
ja |
|
出版者 |
情報処理学会 |
IPSJ-QS21002023.pdf (897.3 kB)
