A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions

• Item type: Trans(1)
• 公開日: 2008-08-27
• タイトル: A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions
• タイトル / 言語: en
• タイトル: A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: System-Level Performance Analysis
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Kyoto University
• 著者所属: PFU Ltd.
• 著者所属: Nara Institute of Science and Technology
• 著者所属(英): en
• 著者所属(英): Kyoto University
• 著者所属(英): en
• 著者所属(英): PFU Ltd.
• 著者所属(英): en
• 著者所属(英): Nara Institute of Science and Technology
• 著者名: Hiroshi, Nakashima; Masahiro, Konishi; Takashi, Nakada
• 著者名(英): Hiroshi, Nakashima; Masahiro, Konishi; Takashi, Nakada
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: This paper proposes an efficient method to analyze the worst case interruption delay (WCID) of a workload running on modern microprocessors using a cycle accurate simulator (CAS). Our method is highly accurate because it simulates all possible cases inserting an interruption just before the retirement of every instruction executed in a workload. It is also (reasonably) efficient because it takes O(N log N) time for a workload with N executed instructions instead of O(N2) of a straightforward iterative simulation of interrupted executions. The key idea for the efficiency is that a pair of executions with different interruption points has a set of durations in which they behave exactly coherent and thus one of simulations for the durations may be omitted. We implemented this method modifying the SimpleScalar tool set to prove it finds out WCID of workloads with five million executed instructions in reasonable time less than 30 minutes which would be 200-300 days by the straightforward method. Furthermore our CAS-based analyzer may have a post process to calculate the WCID for multiple F interrupts with O(FN√N log N) time complexity.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: This paper proposes an efficient method to analyze the worst case interruption delay (WCID) of a workload running on modern microprocessors using a cycle accurate simulator (CAS). Our method is highly accurate because it simulates all possible cases inserting an interruption just before the retirement of every instruction executed in a workload. It is also (reasonably) efficient because it takes O(N log N) time for a workload with N executed instructions, instead of O(N2) of a straightforward iterative simulation of interrupted executions. The key idea for the efficiency is that a pair of executions with different interruption points has a set of durations in which they behave exactly coherent and thus one of simulations for the durations may be omitted. We implemented this method modifying the SimpleScalar tool set to prove it finds out WCID of workloads with five million executed instructions in reasonable time, less than 30 minutes, which would be 200-300 days by the straightforward method. Furthermore, our CAS-based analyzer may have a post process to calculate the WCID for multiple F interrupts with O(FN√N log N) time complexity.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 1, p. 33-47, 発行日 2008-08-27
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会