{"created":"2025-01-18T22:51:18.615822+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00018623","sets":["934:1160:1161"]},"path":["1161"],"owner":"1","recid":"18623","title":["A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions"],"pubdate":{"attribute_name":"公開日","attribute_value":"2008-08-27"},"_buckets":{"deposit":"6b5143bd-5751-445a-9e2b-a7e9540ff013"},"_deposit":{"id":"18623","pid":{"type":"depid","value":"18623","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions"},{"subitem_title":"A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"System-Level Performance Analysis","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2008-08-27","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Kyoto University"},{"subitem_text_value":"PFU Ltd."},{"subitem_text_value":"Nara Institute of Science and Technology"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"PFU Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Nara Institute of Science and Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/18623/files/IPSJ-TSLDM0100004.pdf"},"date":[{"dateType":"Available","dateValue":"2008-08-27"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0100004.pdf","filesize":[{"value":"677.2 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"fe9dbfd5-db13-4c08-a9e3-0b0514776050","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2008 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hiroshi, Nakashima"},{"creatorName":"Masahiro, Konishi"},{"creatorName":"Takashi, Nakada"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hiroshi, Nakashima","creatorNameLang":"en"},{"creatorName":"Masahiro, Konishi","creatorNameLang":"en"},{"creatorName":"Takashi, Nakada","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12394951","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6687","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"This paper proposes an efficient method to analyze the worst case interruption delay (WCID) of a workload running on modern microprocessors using a cycle accurate simulator (CAS). Our method is highly accurate because it simulates all possible cases inserting an interruption just before the retirement of every instruction executed in a workload. It is also (reasonably) efficient because it takes O(N log N) time for a workload with N executed instructions  instead of O(N2) of a straightforward iterative simulation of interrupted executions. The key idea for the efficiency is that a pair of executions with different interruption points has a set of durations in which they behave exactly coherent and thus one of simulations for the durations may be omitted. We implemented this method modifying the SimpleScalar tool set to prove it finds out WCID of workloads with five million executed instructions in reasonable time  less than 30 minutes  which would be 200-300 days by the straightforward method. Furthermore  our CAS-based analyzer may have a post process to calculate the WCID for multiple F interrupts with O(FN√N log N) time complexity.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper proposes an efficient method to analyze the worst case interruption delay (WCID) of a workload running on modern microprocessors using a cycle accurate simulator (CAS). Our method is highly accurate because it simulates all possible cases inserting an interruption just before the retirement of every instruction executed in a workload. It is also (reasonably) efficient because it takes O(N log N) time for a workload with N executed instructions, instead of O(N2) of a straightforward iterative simulation of interrupted executions. The key idea for the efficiency is that a pair of executions with different interruption points has a set of durations in which they behave exactly coherent and thus one of simulations for the durations may be omitted. We implemented this method modifying the SimpleScalar tool set to prove it finds out WCID of workloads with five million executed instructions in reasonable time, less than 30 minutes, which would be 200-300 days by the straightforward method. Furthermore, our CAS-based analyzer may have a post process to calculate the WCID for multiple F interrupts with O(FN√N log N) time complexity.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"47","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology （TSLDM）"}],"bibliographicPageStart":"33","bibliographicIssueDates":{"bibliographicIssueDate":"2008-08-27","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"1"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"links":{},"id":18623,"updated":"2025-01-22T22:38:23.671200+00:00"}