Mask Manufacturability Aware Post OPC Algorithm For Optical Lithography

• Item type: Symposium(1)
• 公開日: 2015-08-19
• タイトル: Mask Manufacturability Aware Post OPC Algorithm For Optical Lithography
• タイトル / 言語: en
• タイトル: Mask Manufacturability Aware Post OPC Algorithm For Optical Lithography
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: 物理設計・回路設計
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_5794
• 資源タイプ: conference paper
• 著者所属: Tokyo Institute of Technology
• 著者所属: Tokyo Institute of Technology
• 著者所属(英): en
• 著者所属(英): Tokyo Institute of Technology
• 著者所属(英): en
• 著者所属(英): Tokyo Institute of Technology
• 著者名: Ahmed, Awad; Atsushi, Takahashi
• 著者名(英): Ahmed, Awad; Atsushi, Takahashi
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: As technology nodes continue scaling down into sub-20nm features, aggressive Optical Proximity Correction (OPC) is the main stream to preserve feature fidelity in silicon wafer for the foreseeable future of optical micro-lithography. Although high level of aggressiveness during OPC is required for better circuit performance in terms of timing and power, it results in complex mask patterns which is directly proportional to mask manufacturability costs, such as, mask writing time and mask data volume. Furthermore, unfriendly litho-patterns might lead to hot spots after OPC. To consider mask manufacturability, several algorithms have been proposed in the field of design aware OPC. In some algorithms, intensive timing and power study on the target circuit is applied prior to OPC to recognize critical regions on which strict OPC is applied while relaxed OPC is applied on the other regions. Other algorithms push the trade-off between mask manufacturability and circuit performance in favor of mask manufacturability, sacrificing parametric yield, through adding a set of restricted design rules to be taken into consideration during OPC response. However, for advanced small-sized dense layouts, design aware OPC algorithms should be executed carefully to ensure pattern fidelity without causing circuit malfunction or significant performance degradation. Therefore, in this paper, we propose a new post processing algorithm, whose objective is to minimize OPCed mask manufacturability costs with pattern fidelity and process window preservation. Our algorithm considers features spacing, mask notch, assisting features dimensions and jogs as design rules whose violations are penalized in a cost function that the algorithm aims to minimize subjected to the constraints that preserve circuit performance within its allowable tolerance.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: As technology nodes continue scaling down into sub-20nm features, aggressive Optical Proximity Correction (OPC) is the main stream to preserve feature fidelity in silicon wafer for the foreseeable future of optical micro-lithography. Although high level of aggressiveness during OPC is required for better circuit performance in terms of timing and power, it results in complex mask patterns which is directly proportional to mask manufacturability costs, such as, mask writing time and mask data volume. Furthermore, unfriendly litho-patterns might lead to hot spots after OPC. To consider mask manufacturability, several algorithms have been proposed in the field of design aware OPC. In some algorithms, intensive timing and power study on the target circuit is applied prior to OPC to recognize critical regions on which strict OPC is applied while relaxed OPC is applied on the other regions. Other algorithms push the trade-off between mask manufacturability and circuit performance in favor of mask manufacturability, sacrificing parametric yield, through adding a set of restricted design rules to be taken into consideration during OPC response. However, for advanced small-sized dense layouts, design aware OPC algorithms should be executed carefully to ensure pattern fidelity without causing circuit malfunction or significant performance degradation. Therefore, in this paper, we propose a new post processing algorithm, whose objective is to minimize OPCed mask manufacturability costs with pattern fidelity and process window preservation. Our algorithm considers features spacing, mask notch, assisting features dimensions and jogs as design rules whose violations are penalized in a cost function that the algorithm aims to minimize subjected to the constraints that preserve circuit performance within its allowable tolerance.
• 書誌情報: DAシンポジウム2015論文集; 巻 2015, p. 119-124, 発行日 2015-08-19
• 出版者 / 言語: ja
• 出版者: 情報処理学会