| Item type |
Trans(1) |
| 公開日 |
2015-08-01 |
| タイトル |
|
|
タイトル |
DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework |
| タイトル |
|
|
言語 |
en |
|
タイトル |
DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework |
| 言語 |
|
|
言語 |
eng |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
[Architectural Design] DRAM, modelling, TLM2, memory subsystem, controller, optimisation |
| 資源タイプ |
|
|
資源タイプ識別子 |
http://purl.org/coar/resource_type/c_6501 |
|
資源タイプ |
journal article |
| 著者所属 |
|
|
|
University of Kaiserslautern |
| 著者所属 |
|
|
|
University of Kaiserslautern |
| 著者所属 |
|
|
|
University of Kaiserslautern |
| 著者所属(英) |
|
|
|
en |
|
|
University of Kaiserslautern |
| 著者所属(英) |
|
|
|
en |
|
|
University of Kaiserslautern |
| 著者所属(英) |
|
|
|
en |
|
|
University of Kaiserslautern |
| 著者名 |
Matthias, Jung
Christian, Weis
Norbert, Wehn
|
| 著者名(英) |
Matthias, Jung
Christian, Weis
Norbert, Wehn
|
| 論文抄録 |
|
|
内容記述タイプ |
Other |
|
内容記述 |
In systems ranging from mobile devices to servers, Dynamic Random Access Memories (DRAM) have a big impact on performance and contributes a significant part of the total consumed power. Conventional DDR3-based solutions are stretched thin as their maximum bandwidth is limited by the I/O count and interface speed. As new solutions are coming onto the market (JEDEC DDR4, JEDEC WIDE I/O, Micron's hybrid memory cube: HMC or JEDEC's high bandwidth memory: HBM) it is critical to evaluate the performance of these solutions and assess their suitability for specific applications. Furthermore, in systems with 3D stacking, the challenges of high power densities and thermal dissipation are exacerbated. It is crucial to have a flexible and holistic DRAM subsystem framework for exhaustive design space explorations, which can handle all this different types of memories, as well as the aspects of performance, power and temperature. |
| 論文抄録(英) |
|
|
内容記述タイプ |
Other |
|
内容記述 |
In systems ranging from mobile devices to servers, Dynamic Random Access Memories (DRAM) have a big impact on performance and contributes a significant part of the total consumed power. Conventional DDR3-based solutions are stretched thin as their maximum bandwidth is limited by the I/O count and interface speed. As new solutions are coming onto the market (JEDEC DDR4, JEDEC WIDE I/O, Micron's hybrid memory cube: HMC or JEDEC's high bandwidth memory: HBM) it is critical to evaluate the performance of these solutions and assess their suitability for specific applications. Furthermore, in systems with 3D stacking, the challenges of high power densities and thermal dissipation are exacerbated. It is crucial to have a flexible and holistic DRAM subsystem framework for exhaustive design space explorations, which can handle all this different types of memories, as well as the aspects of performance, power and temperature. |
| 書誌レコードID |
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|
収録物識別子タイプ |
NCID |
|
収録物識別子 |
AA12394951 |
| 書誌情報 |
IPSJ Transactions on System LSI Design Methodology （TSLDM）
巻 8,
p. 63-74,
発行日 2015-08-01
|
| ISSN |
|
|
収録物識別子タイプ |
ISSN |
|
収録物識別子 |
1882-6687 |
| 出版者 |
|
|
言語 |
ja |
|
出版者 |
情報処理学会 |
IPSJ-TSLDM0800008.pdf (4.3 MB)
