{"id":144665,"updated":"2025-01-20T18:43:34.418871+00:00","links":{},"created":"2025-01-19T00:20:25.216704+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00144665","sets":["934:1160:7888"]},"path":["7888"],"owner":"11","recid":"144665","title":["DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-08-01"},"_buckets":{"deposit":"d4b8cc03-c4bd-4f95-baa3-0a033fc16ca7"},"_deposit":{"id":"144665","pid":{"type":"depid","value":"144665","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework","author_link":["219550","219548","219551","219549","219553","219552"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework"},{"subitem_title":"DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"[Architectural Design] DRAM, modelling, TLM2, memory subsystem, controller, optimisation","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2015-08-01","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"University of Kaiserslautern"},{"subitem_text_value":"University of Kaiserslautern"},{"subitem_text_value":"University of Kaiserslautern"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"University of Kaiserslautern","subitem_text_language":"en"},{"subitem_text_value":"University of Kaiserslautern","subitem_text_language":"en"},{"subitem_text_value":"University of Kaiserslautern","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/144665/files/IPSJ-TSLDM0800008.pdf","label":"IPSJ-TSLDM0800008.pdf"},"date":[{"dateType":"Available","dateValue":"2015-08-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0800008.pdf","filesize":[{"value":"4.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"76bf3643-9909-4a33-86ec-747d7b1eb42e","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2015 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Matthias, Jung"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Christian, Weis"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Norbert, Wehn"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Matthias, Jung","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Christian, Weis","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Norbert, Wehn","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12394951","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6687","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"In systems ranging from mobile devices to servers, Dynamic Random Access Memories (DRAM) have a big impact on performance and contributes a significant part of the total consumed power. Conventional DDR3-based solutions are stretched thin as their maximum bandwidth is limited by the I/O count and interface speed. As new solutions are coming onto the market (JEDEC DDR4, JEDEC WIDE I/O, Micron's hybrid memory cube: HMC or JEDEC's high bandwidth memory: HBM) it is critical to evaluate the performance of these solutions and assess their suitability for specific applications. Furthermore, in systems with 3D stacking, the challenges of high power densities and thermal dissipation are exacerbated. It is crucial to have a flexible and holistic DRAM subsystem framework for exhaustive design space explorations, which can handle all this different types of memories, as well as the aspects of performance, power and temperature.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In systems ranging from mobile devices to servers, Dynamic Random Access Memories (DRAM) have a big impact on performance and contributes a significant part of the total consumed power. Conventional DDR3-based solutions are stretched thin as their maximum bandwidth is limited by the I/O count and interface speed. As new solutions are coming onto the market (JEDEC DDR4, JEDEC WIDE I/O, Micron's hybrid memory cube: HMC or JEDEC's high bandwidth memory: HBM) it is critical to evaluate the performance of these solutions and assess their suitability for specific applications. Furthermore, in systems with 3D stacking, the challenges of high power densities and thermal dissipation are exacerbated. It is crucial to have a flexible and holistic DRAM subsystem framework for exhaustive design space explorations, which can handle all this different types of memories, as well as the aspects of performance, power and temperature.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"74","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology （TSLDM）"}],"bibliographicPageStart":"63","bibliographicIssueDates":{"bibliographicIssueDate":"2015-08-01","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"8"}]},"relation_version_is_last":true,"weko_creator_id":"11"}}