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Architecture of an AI Processor Chip (IP1704)
https://ipsj.ixsq.nii.ac.jp/records/59748
https://ipsj.ixsq.nii.ac.jp/records/597486941bc6d-4ee1-4c7c-853e-e455ba4e52e3
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
IPSJ-JIP1302005.pdf (783.6 kB)
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Copyright (c) 1990 by the Information Processing Society of Japan
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| オープンアクセス | ||
| Item type | JInfP(1) | |||||||
|---|---|---|---|---|---|---|---|---|
| 公開日 | 1990-08-25 | |||||||
| タイトル | ||||||||
| タイトル | Architecture of an AI Processor Chip (IP1704) | |||||||
| タイトル | ||||||||
| 言語 | en | |||||||
| タイトル | Architecture of an AI Processor Chip (IP1704) | |||||||
| 言語 | ||||||||
| 言語 | eng | |||||||
| 資源タイプ | ||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||
| 資源タイプ | journal article | |||||||
| 著者所属 | ||||||||
| Information Systems Laboratory Toshiba Research and Development Center Toshiba Corporation | ||||||||
| 著者所属 | ||||||||
| Information Systems Laboratory Toshiba Research and Development Center Toshiba Corporation | ||||||||
| 著者所属 | ||||||||
| Information Systems Laboratory Toshiba Research and Development Ce | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Information Systems Laboratory, Toshiba Research and Development Center, Toshiba Corporation | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Information Systems Laboratory, Toshiba Research and Development Center, Toshiba Corporation | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Information Systems Laboratory, Toshiba Research and Development Ce | ||||||||
| 著者名 |
Mitsuo, Saito
× Mitsuo, Saito
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| 著者名(英) |
Mitsuo, Saito
× Mitsuo, Saito
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| 論文抄録 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | The CPU of the AI processor (AIP) called IP704 was developed for Prolog and Lisp based on RISC architecture with hardware supports. It has been proved that IP704 architecture is effective for both AI languages and general-purpose languages. An AI processor chip (IP 1704) is being developed as a direct successor of the IP704. The architecture has been modified and refined to fit onto a single chip and to improve the execution speed. Features newly developed for the IP1704 include Overlapping of the decode and register-read stages using a combination of the hardware decoder and micro-programs and a delayed cache hit check with delayed writing. Is shown that a RISC-based processor with suitable hardware support is applicable to VLSI and also gives high performance AI languages. | |||||||
| 論文抄録(英) | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | The CPU of the AI processor (AIP) called IP704 was developed for Prolog and Lisp, based on RISC architecture with hardware supports. It has been proved that IP704 architecture is effective for both AI languages and general-purpose languages. An AI processor chip (IP 1704) is being developed as a direct successor of the IP704. The architecture has been modified and refined to fit onto a single chip and to improve the execution speed. Features newly developed for the IP1704 include Overlapping of the decode and register-read stages using a combination of the hardware decoder and micro-programs, and a delayed cache hit check with delayed writing. Is shown that a RISC-based processor with suitable hardware support is applicable to VLSI and also gives high performance AI languages. | |||||||
| 書誌レコードID | ||||||||
| 収録物識別子タイプ | NCID | |||||||
| 収録物識別子 | AA00700121 | |||||||
| 書誌情報 |
Journal of Information Processing 巻 13, 号 2, p. 144-149, 発行日 1990-08-25 |
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| ISSN | ||||||||
| 収録物識別子タイプ | ISSN | |||||||
| 収録物識別子 | 1882-6652 | |||||||
| 出版者 | ||||||||
| 言語 | ja | |||||||
| 出版者 | 情報処理学会 | |||||||
