{"id":59748,"updated":"2025-01-22T03:26:47.950250+00:00","links":{},"created":"2025-01-18T23:22:27.497184+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00059748","sets":["5471:5485:5488"]},"path":["5488"],"owner":"1","recid":"59748","title":["Architecture of an AI Processor Chip (IP1704)"],"pubdate":{"attribute_name":"公開日","attribute_value":"1990-08-25"},"_buckets":{"deposit":"29794ac5-b904-4ab8-ae8f-6dfd4208dd9c"},"_deposit":{"id":"59748","pid":{"type":"depid","value":"59748","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"Architecture of an AI Processor Chip (IP1704)","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Architecture of an AI Processor Chip (IP1704)"},{"subitem_title":"Architecture of an AI Processor Chip (IP1704)","subitem_title_language":"en"}]},"item_type_id":"5","publish_date":"1990-08-25","item_5_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Information Systems Laboratory Toshiba Research and Development Center Toshiba Corporation"},{"subitem_text_value":"Information Systems Laboratory Toshiba Research and Development Center Toshiba Corporation"},{"subitem_text_value":"Information Systems Laboratory Toshiba Research and Development Ce"}]},"item_5_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Information Systems Laboratory, Toshiba Research and Development Center, Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Information Systems Laboratory, Toshiba Research and Development Center, Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Information Systems Laboratory, Toshiba Research and Development Ce","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/59748/files/IPSJ-JIP1302005.pdf"},"date":[{"dateType":"Available","dateValue":"1992-08-25"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JIP1302005.pdf","filesize":[{"value":"783.6 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"2a382175-f199-4d58-b528-1dd0dadfd540","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1990 by the Information Processing Society of Japan"}]},"item_5_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Mitsuo, Saito"},{"creatorName":"Takeshi, Aikawa"},{"creatorName":"Tsukasa, Matoba"},{"creatorName":"Mitsuyoshi, Okamura"},{"creatorName":"Kenji, Minagawa"},{"creatorName":"Tadatoshi, Ishii"}],"nameIdentifiers":[{}]}]},"item_5_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Mitsuo, Saito","creatorNameLang":"en"},{"creatorName":"Takeshi, Aikawa","creatorNameLang":"en"},{"creatorName":"Tsukasa, Matoba","creatorNameLang":"en"},{"creatorName":"Mitsuyoshi, Okamura","creatorNameLang":"en"},{"creatorName":"Kenji, Minagawa","creatorNameLang":"en"},{"creatorName":"Tadatoshi, Ishii","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_5_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA00700121","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_5_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6652","subitem_source_identifier_type":"ISSN"}]},"item_5_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"The CPU of the AI processor (AIP) called IP704 was developed for Prolog and Lisp based on RISC architecture with hardware supports. It has been proved that IP704 architecture is effective for both AI languages and general-purpose languages. An AI processor chip (IP 1704) is being developed as a direct successor of the IP704. The architecture has been modified and refined to fit onto a single chip and to improve the execution speed. Features newly developed for the IP1704 include Overlapping of the decode and register-read stages using a combination of the hardware decoder and micro-programs and a delayed cache hit check with delayed writing. Is shown that a RISC-based processor with suitable hardware support is applicable to VLSI and also gives high performance AI languages.","subitem_description_type":"Other"}]},"item_5_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The CPU of the AI processor (AIP) called IP704 was developed for Prolog and Lisp, based on RISC architecture with hardware supports. It has been proved that IP704 architecture is effective for both AI languages and general-purpose languages. An AI processor chip (IP 1704) is being developed as a direct successor of the IP704. The architecture has been modified and refined to fit onto a single chip and to improve the execution speed. Features newly developed for the IP1704 include Overlapping of the decode and register-read stages using a combination of the hardware decoder and micro-programs, and a delayed cache hit check with delayed writing. Is shown that a RISC-based processor with suitable hardware support is applicable to VLSI and also gives high performance AI languages.","subitem_description_type":"Other"}]},"item_5_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"149","bibliographic_titles":[{"bibliographic_title":"Journal of Information Processing "}],"bibliographicPageStart":"144","bibliographicIssueDates":{"bibliographicIssueDate":"1990-08-25","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2","bibliographicVolumeNumber":"13"}]},"relation_version_is_last":true,"weko_creator_id":"1"}}