A Behavior-based Adaptive Access-mode for Low-power Set-associative Caches in Embedded Systems

• Item type: Journal(1)
• 公開日: 2011-12-15
• タイトル: A Behavior-based Adaptive Access-mode for Low-power Set-associative Caches in Embedded Systems
• タイトル / 言語: en
• タイトル: A Behavior-based Adaptive Access-mode for Low-power Set-associative Caches in Embedded Systems
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: 特集：組込みシステム工学
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Graduate School of Information, Production and Systems, Waseda University
• 著者所属: Graduate School of Information, Production and Systems, Waseda University
• 著者所属: Graduate School of Information, Production and Systems, Waseda University
• 著者所属: Graduate School of Information, Production and Systems, Waseda University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information, Production and Systems, Waseda University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information, Production and Systems, Waseda University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information, Production and Systems, Waseda University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information, Production and Systems, Waseda University
• 著者名: Jiongyao, Ye; Hongfeng, Ding; Yingtao, Hu; Takahiro, Watanabe
• 著者名(英): Jiongyao, Ye; Hongfeng, Ding; Yingtao, Hu; Takahiro, Watanabe
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Modern embedded processors commonly use a set-associative scheme to reduce cache misses. However, a conventional set-associative cache has its drawbacks in terms of power consumption because it has to probe all ways to reduce the access time, although only the matched way is used. The energy spent in accessing the other ways is wasted, and the percentage of such energy will increase as cache associativity increases. Previous research, such as phased caches, way prediction caches and partial tag comparison, have been proposed to reduce the power consumption of set-associative caches by optimizing the cache access mode. However, these methods are not adaptable according to the program behavior because of using a single access mode throughout the program execution. In this paper, we propose a behavior-based adaptive access-mode for set-associative caches in embedded systems, which can dynamically adjust the access modes during the program execution. First, a program is divided into several phases based on the principle of program behavior repetition. Then, an off-system pre-analysis is used to exploit the optimal access mode for each phase so that each phase employs the different optimal access mode to meet the application's demand during the program execution. Our proposed approach requires little hardware overhead and commits most workload to the software, so it is very effective for embedded processors. Simulation by using Spec 2000 shows that our proposed approach can reduce roughly 76.95% and 64.67% of power for an instruction cache and a data cache, respectively. At the same time, the performance degradation is less than 1%.; ------------------------------; This is a preprint of an article intended for publication Journal of; Information Processing(JIP). This preprint should not be cited. This; article should be cited as: Journal of Information Processing Vol.20(2012) No.1 (online); DOI http://dx.doi.org/10.2197/ipsjjip.20.26; ------------------------------
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Modern embedded processors commonly use a set-associative scheme to reduce cache misses. However, a conventional set-associative cache has its drawbacks in terms of power consumption because it has to probe all ways to reduce the access time, although only the matched way is used. The energy spent in accessing the other ways is wasted, and the percentage of such energy will increase as cache associativity increases. Previous research, such as phased caches, way prediction caches and partial tag comparison, have been proposed to reduce the power consumption of set-associative caches by optimizing the cache access mode. However, these methods are not adaptable according to the program behavior because of using a single access mode throughout the program execution. In this paper, we propose a behavior-based adaptive access-mode for set-associative caches in embedded systems, which can dynamically adjust the access modes during the program execution. First, a program is divided into several phases based on the principle of program behavior repetition. Then, an off-system pre-analysis is used to exploit the optimal access mode for each phase so that each phase employs the different optimal access mode to meet the application's demand during the program execution. Our proposed approach requires little hardware overhead and commits most workload to the software, so it is very effective for embedded processors. Simulation by using Spec 2000 shows that our proposed approach can reduce roughly 76.95% and 64.67% of power for an instruction cache and a data cache, respectively. At the same time, the performance degradation is less than 1%.; ------------------------------; This is a preprint of an article intended for publication Journal of; Information Processing(JIP). This preprint should not be cited. This; article should be cited as: Journal of Information Processing Vol.20(2012) No.1 (online); DOI http://dx.doi.org/10.2197/ipsjjip.20.26; ------------------------------
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN00116647
• 書誌情報: 情報処理学会論文誌; 巻 52, 号 12, 発行日 2011-12-15
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-7764