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  1. JIP
  2. Vol.1
  3. No.1

Analysis of Parallel Hashing Algorithms with Key Deletion

https://ipsj.ixsq.nii.ac.jp/records/60040
https://ipsj.ixsq.nii.ac.jp/records/60040
c5c25adc-0aff-4a64-97b4-64b9e5c5be7b
名前 / ファイル ライセンス アクション
IPSJ-JIP0101005.pdf IPSJ-JIP0101005 (953.0 kB)
Copyright (c) 1978 by the Information Processing Society of Japan
オープンアクセス
Item type JInfP(1)
公開日 1978-04-20
タイトル
タイトル Analysis of Parallel Hashing Algorithms with Key Deletion
タイトル
言語 en
タイトル Analysis of Parallel Hashing Algorithms with Key Deletion
言語
言語 eng
キーワード
主題Scheme Other
主題 (IPSJ Best Paper Award、論文賞受賞)
資源タイプ
資源タイプ識別子 http://purl.org/coar/resource_type/c_6501
資源タイプ journal article
著者所属
Institute of Physical and Chemical Research 2-1
著者所属
Department of Information Science University of Tokyo
著者所属(英)
en
Institute of Physical and Chemical Research 2-1
著者所属(英)
en
Institute of Physical and Chemical Research 2-1/Department of Information Science University of Tokyo
著者名 Tetsuo, Ida

× Tetsuo, Ida

Tetsuo, Ida

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Eiichi, Goto

× Eiichi, Goto

Eiichi, Goto

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著者名(英) Tetsuo, Ida

× Tetsuo, Ida

en Tetsuo, Ida

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Eiichi, Goto

× Eiichi, Goto

en Eiichi, Goto

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論文抄録
内容記述タイプ Other
内容記述 Three parallel hashing schemes are presented together with the analysis of their efficiencies based on a statistical theory. As assesment parameters probe numbers for parallel hash algorithms in these schemes such as for pure search and for key insertion are calculated in the worst statistical equilibrium. The results show improvement of the efficiencies of parallel hash algorithms over those of conventional sequential hashing. When parallel hash algorithms are implemented in hardware with multi-bank memory they can be executed in a time comparable to single indirect addressing.
論文抄録(英)
内容記述タイプ Other
内容記述 Three parallel hashing schemes are presented together with the analysis of their efficiencies based on a statistical theory. As assesment parameters, probe numbers for parallel hash algorithms in these schemes such as for pure search and for key insertion are calculated in the worst statistical equilibrium. The results show improvement of the efficiencies of parallel hash algorithms over those of conventional sequential hashing. When parallel hash algorithms are implemented in hardware with multi-bank memory, they can be executed in a time comparable to single indirect addressing.
書誌レコードID
収録物識別子タイプ NCID
収録物識別子 AA00700121
書誌情報 Journal of Information Processing

巻 1, 号 1, p. 25-32, 発行日 1978-04-20
ISSN
収録物識別子タイプ ISSN
収録物識別子 1882-6652
出版者
言語 ja
出版者 情報処理学会
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