WEKO3
アイテム
画像生成用マルチコンピュータシステムとプロセッサについて
https://ipsj.ixsq.nii.ac.jp/records/39179
https://ipsj.ixsq.nii.ac.jp/records/391793bd9ad80-cf34-4625-8ee4-062f0dee7fc9
名前 / ファイル | ライセンス | アクション |
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Copyright (c) 1985 by the Information Processing Society of Japan
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オープンアクセス |
Item type | SIG Technical Reports(1) | |||||||
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公開日 | 1985-10-25 | |||||||
タイトル | ||||||||
タイトル | 画像生成用マルチコンピュータシステムとプロセッサについて | |||||||
タイトル | ||||||||
言語 | en | |||||||
タイトル | Image Generation Multicomputer System and the Processors | |||||||
言語 | ||||||||
言語 | jpn | |||||||
資源タイプ | ||||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_18gh | |||||||
資源タイプ | technical report | |||||||
著者所属 | ||||||||
大阪大学工学部電子工学科 | ||||||||
著者所属 | ||||||||
大阪大学工学部電子工学科 | ||||||||
著者所属 | ||||||||
大阪大学工学部電子工学科 | ||||||||
著者所属 | ||||||||
大阪大学工学部電子工学科:(現)(株)トーヨーリンクス | ||||||||
著者所属 | ||||||||
大阪大学工学部電子工学科 | ||||||||
著者所属 | ||||||||
大阪大学工学部電子工学科 | ||||||||
著者所属 | ||||||||
大阪大学工学部電子工学科 | ||||||||
著者所属 | ||||||||
大阪大学工学部電子工学科 | ||||||||
著者所属 | ||||||||
大阪大学工学部電子工学科 | ||||||||
著者所属(英) | ||||||||
en | ||||||||
OSAKA University Faculity of Engineering Department of Electronic Engineering | ||||||||
著者所属(英) | ||||||||
en | ||||||||
OSAKA University Faculity of Engineering Department of Electronic Engineering | ||||||||
著者所属(英) | ||||||||
en | ||||||||
OSAKA University Faculity of Engineering Department of Electronic Engineering | ||||||||
著者所属(英) | ||||||||
en | ||||||||
(Present address) Toyo Links Co. | ||||||||
著者所属(英) | ||||||||
en | ||||||||
OSAKA University Faculity of Engineering Department of Electronic Engineering | ||||||||
著者所属(英) | ||||||||
en | ||||||||
OSAKA University Faculity of Engineering Department of Electronic Engineering | ||||||||
著者所属(英) | ||||||||
en | ||||||||
OSAKA University Faculity of Engineering Department of Electronic Engineering | ||||||||
著者所属(英) | ||||||||
en | ||||||||
OSAKA University Faculity of Engineering Department of Electronic Engineering | ||||||||
著者所属(英) | ||||||||
en | ||||||||
OSAKA University Faculity of Engineering Department of Electronic Engineering | ||||||||
著者名 |
河合, 利幸
若井, 裕久
正田, 博司
西村, 仁志
近藤, 仁志
高山, 浩一郎
出口, 弘
白川, 功
大村皓一
× 河合, 利幸 若井, 裕久 正田, 博司 西村, 仁志 近藤, 仁志 高山, 浩一郎 出口, 弘 白川, 功 大村皓一
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著者名(英) |
Toshiyuki, Kawai
Hirohisa, Wakai
Hiroshi, Shoda
Hitoshi, Nishimura
Hitoshi, Kondo
Koichiro, Takayama
Hiroshi, Deguchi
Isao, Shirakawa
Koichi, Omura
× Toshiyuki, Kawai Hirohisa, Wakai Hiroshi, Shoda Hitoshi, Nishimura Hitoshi, Kondo Koichiro, Takayama Hiroshi, Deguchi Isao, Shirakawa Koichi, Omura
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論文抄録 | ||||||||
内容記述タイプ | Other | |||||||
内容記述 | A great number of approaches have been proposed to 3D image generation among which a prallel processing implementation is believed to be most promising. Motivated by this we have developed a 3D image generation scheme on parallel multicomputer system LINKS-1. Based on a variety of experimental results on it a more powerful system is under development to improve efficiency of 3D image generation. In this paper this new system is described stressing the hardware configuration. It is distinctive in that a unit computer is composed of a data processing unit performing 32 bit floating point operations at the speed of 5 MFLOPS an index unit performing addressing operations a channel processor for communication control etc. Performance evaluations are also estimated. | |||||||
論文抄録(英) | ||||||||
内容記述タイプ | Other | |||||||
内容記述 | A great number of approaches have been proposed to 3D image generation, among which a prallel processing implementation is believed to be most promising. Motivated by this, we have developed a 3D image generation scheme on parallel multicomputer system LINKS-1. Based on a variety of experimental results on it, a more powerful system is under development to improve efficiency of 3D image generation. In this paper this new system is described, stressing the hardware configuration. It is distinctive in that a unit computer is composed of a data processing unit performing 32 bit floating point operations at the speed of 5 MFLOPS, an index unit performing addressing operations, a channel processor for communication control, etc. Performance evaluations are also estimated. | |||||||
書誌レコードID | ||||||||
収録物識別子タイプ | NCID | |||||||
収録物識別子 | AN10100541 | |||||||
書誌情報 |
情報処理学会研究報告グラフィクスとCAD(CG) 巻 1985, 号 44(1985-CG-019), p. 1-7, 発行日 1985-10-25 |
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Notice | ||||||||
SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc. | ||||||||
出版者 | ||||||||
言語 | ja | |||||||
出版者 | 情報処理学会 |