| Item type |
SIG Technical Reports(1) |
| 公開日 |
2024-06-03 |
| タイトル |
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|
タイトル |
Preliminary Report on an FPGA-based Prototype of a Network Switch Supporting Asynchronous Traffic Shaping for Time Sensitive Networking |
| タイトル |
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言語 |
en |
|
タイトル |
Preliminary Report on an FPGA-based Prototype of a Network Switch Supporting Asynchronous Traffic Shaping for Time Sensitive Networking |
| 言語 |
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|
言語 |
eng |
| キーワード |
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|
主題Scheme |
Other |
|
主題 |
通信 |
| 資源タイプ |
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資源タイプ識別子 |
http://purl.org/coar/resource_type/c_18gh |
|
資源タイプ |
technical report |
| 著者所属 |
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|
Digital Architecture Research Center National Institute of Advanced Industrial Sciences and Technology |
| 著者所属 |
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Digital Architecture Research Center National Institute of Advanced Industrial Sciences and Technology |
| 著者所属 |
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Digital Architecture Research Center National Institute of Advanced Industrial Sciences and Technology |
| 著者所属(英) |
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|
en |
|
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Digital Architecture Research Center National Institute of Advanced Industrial Sciences and Technology |
| 著者所属(英) |
|
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|
en |
|
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Digital Architecture Research Center National Institute of Advanced Industrial Sciences and Technology |
| 著者所属(英) |
|
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|
en |
|
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Digital Architecture Research Center National Institute of Advanced Industrial Sciences and Technology |
| 著者名 |
Akram, Ben Ahmed
Takahiro, Hirofuchi
Takaaki, Fukai
|
| 著者名(英) |
Akram, Ben Ahmed
Takahiro, Hirofuchi
Takaaki, Fukai
|
| 論文抄録 |
|
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内容記述タイプ |
Other |
|
内容記述 |
Time Sensitive Networking (TSN) is an additional set of new open standards to conventional IEEE 802.3 Ethernet networks that aims to provide deterministic, reliable, high-bandwidth and low-latency communication. In this paper, we present an initial architecture of an FPGA-based network switch supporting Asynchronous Traffic Shaping (ATS) for Time Sensitive Networking. We present the key architectural components and implementation aspects of the proposed switch and discuss the preliminary evaluation results in a fair amount of details to validate our proposal. The conducted experiments confirm that the proposed switch executes the proper burst and rate control management, and that our arrival rate and arrival frame interval evaluation results are conform with the ATS theoretical model. |
| 論文抄録(英) |
|
|
内容記述タイプ |
Other |
|
内容記述 |
Time Sensitive Networking (TSN) is an additional set of new open standards to conventional IEEE 802.3 Ethernet networks that aims to provide deterministic, reliable, high-bandwidth and low-latency communication. In this paper, we present an initial architecture of an FPGA-based network switch supporting Asynchronous Traffic Shaping (ATS) for Time Sensitive Networking. We present the key architectural components and implementation aspects of the proposed switch and discuss the preliminary evaluation results in a fair amount of details to validate our proposal. The conducted experiments confirm that the proposed switch executes the proper burst and rate control management, and that our arrival rate and arrival frame interval evaluation results are conform with the ATS theoretical model. |
| 書誌レコードID |
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収録物識別子タイプ |
NCID |
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収録物識別子 |
AN10096105 |
| 書誌情報 |
研究報告システム・アーキテクチャ（ARC）
巻 2024-ARC-257,
号 8,
p. 1-7,
発行日 2024-06-03
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| ISSN |
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収録物識別子タイプ |
ISSN |
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収録物識別子 |
2188-8574 |
| Notice |
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SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc. |
| 出版者 |
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言語 |
ja |
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出版者 |
情報処理学会 |
IPSJ-ARC24257008.pdf (1.7 MB)
