FPGA Case of Study: Fast Prototyping Methodology for Mixed-Signal Modeling and Integration Based on Open-Source Tools

• Item type: Symposium(1)
• 公開日: 2023-08-23
• タイトル: FPGA Case of Study: Fast Prototyping Methodology for Mixed-Signal Modeling and Integration Based on Open-Source Tools
• タイトル / 言語: en
• タイトル: FPGA Case of Study: Fast Prototyping Methodology for Mixed-Signal Modeling and Integration Based on Open-Source Tools
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: オープンソース設計ツール
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_5794
• 資源タイプ: conference paper
• 著者所属: Systems Design Lab., School of Engineering, The University of Tokyo
• 著者所属: Systems Design Lab., School of Engineering, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Systems Design Lab., School of Engineering, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Systems Design Lab., School of Engineering, The University of Tokyo
• 著者名: Ckristian, Duran; Tetsuya, Iizuka
• 著者名(英): Ckristian, Duran; Tetsuya, Iizuka
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Very-Large Scale Integration (VLSI) of circuits utilizes a series of Electronic Design Automation (EDA) tools to perform synthesis, placement, routing, and verification. Such tools are used with Computer-Aided Design (CAD) software to design analog circuits and the final application chip. Despite this software being optimized for larger chips, many steps in different design methodologies are performed by human labor, increasing the cost of design. Additionally, integration personnel performs the integration flow between analog and digital designs, making the chip integration design prine to errors and cost-ineffective. These problems exist partially because of the obscurity of commercial CAD and EDA software, which allow little customization of such tools. This paper explores a fast prototyping methodology integrating a Field-Programmable Gate Array (FPGA) in a chip design as a case study. The FPGA contains both digital and analog circuits to aid the calculation of neural networks. This FPGA has been designed with open-source tools for architecture prototyping, circuit design, analog testing, I/O and pad frame generation, and overall integrated circuit generation. The described methodology can use commercial tools for placement, routing, and simulation of circuits but can be developed with open-source tools such as OpenLANE. With the use of the described open-source tools, a user has the potential to automate circuit design up to the sign-off stages. We additionally demonstrate fast and cost-efficient verification, such as that the user can apply fixes on several design layers and integration on the fly.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Very-Large Scale Integration (VLSI) of circuits utilizes a series of Electronic Design Automation (EDA) tools to perform synthesis, placement, routing, and verification. Such tools are used with Computer-Aided Design (CAD) software to design analog circuits and the final application chip. Despite this software being optimized for larger chips, many steps in different design methodologies are performed by human labor, increasing the cost of design. Additionally, integration personnel performs the integration flow between analog and digital designs, making the chip integration design prine to errors and cost-ineffective. These problems exist partially because of the obscurity of commercial CAD and EDA software, which allow little customization of such tools. This paper explores a fast prototyping methodology integrating a Field-Programmable Gate Array (FPGA) in a chip design as a case study. The FPGA contains both digital and analog circuits to aid the calculation of neural networks. This FPGA has been designed with open-source tools for architecture prototyping, circuit design, analog testing, I/O and pad frame generation, and overall integrated circuit generation. The described methodology can use commercial tools for placement, routing, and simulation of circuits but can be developed with open-source tools such as OpenLANE. With the use of the described open-source tools, a user has the potential to automate circuit design up to the sign-off stages. We additionally demonstrate fast and cost-efficient verification, such as that the user can apply fixes on several design layers and integration on the fly.
• 書誌情報: DAシンポジウム2023論文集; 巻 2023, p. 90-96, 発行日 2023-08-23
• 出版者 / 言語: ja
• 出版者: 情報処理学会