WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code

• Item type: SIG Technical Reports(1)
• 公開日: 2022-10-20
• タイトル: WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code
• タイトル / 言語: en
• タイトル: WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code
• 言語: eng
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: 東京大学
• 著者所属: NTTコンピュータ& データサイエンス研究所／JSTさきがけ
• 著者所属: 九州大学／JSTさきがけ
• 著者所属: 東京大学
• 著者所属: NTTコンピュータ& データサイエンス研究所
• 著者所属(英): en
• 著者所属(英): the University of Tokyo
• 著者所属(英): en
• 著者所属(英): NTT Computer and Data Science Laboratories / JST, PRESTO
• 著者所属(英): en
• 著者所属(英): Kyushu University / JST, PRESTO
• 著者所属(英): en
• 著者所属(英): the University of Tokyo
• 著者所属(英): en
• 著者所属(英): NTT Computer and Data Science Laboratories
• 著者名: 廖, 望; 鈴木, 泰成; 谷本, 輝夫; 上野, 洋典; 徳永, 裕己
• 著者名(英): Wang, Liao; Yasunari, Suzuki; Teruo, Tanimoto; Yosuke, Ueno; Yuuki, Tokunaga
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Large error rates of quantum bits (qubits) are one of the main difficulties in the development of quantum computing. Performing quantum error correction (QEC) with surface codes is considered the most promising approach to reduce the error rates of qubits effectively. To perform error correction, we need an error-decoding unit, which estimates errors in the noisy physical qubits repetitively, to create a robust logical qubit. While complicated graph-matching problems must be solved within a strict time restriction for the error decoding, several hardware implementations that satisfy the restriction at a large code distance have been proposed. However, the existing decoder designs are still challenging in reducing the logical error rate. This is because they assume that the error rates of physical qubits are uniform while they have large variations in practice. According to our numerical simulation based on the most advanced quantum chip, neglecting the non-uniform error properties of a real quantum chip in the decoding process induces significant degradation of the logical error rate and spoils the benefit of QEC. To take the non-uniformity into account, decoders need to solve matching problems on a weighted graph, but they are difficult to solve using the existing designs without exceeding the time limit of decoding. Therefore, a decoder that can treat both the non-uniform physical error rates and the large surface code is strongly demanded. In this paper, we propose a hardware design of decoding units for the surface code that can treat the non-identical error properties with small latency at a large code distance. The key idea of our design is 1) constructing a look-up table for calculating the shortest paths between nodes in a weighted graph and 2) enabling parallel processing during decoding. The implementation results in field programmable gate array (FPGA) indicate that our design scales up to code distance 11 within a microsecond-level delay, which is comparable to the existing state-of-the-art designs, while our design can treat non-identical errors.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Large error rates of quantum bits (qubits) are one of the main difficulties in the development of quantum computing. Performing quantum error correction (QEC) with surface codes is considered the most promising approach to reduce the error rates of qubits effectively. To perform error correction, we need an error-decoding unit, which estimates errors in the noisy physical qubits repetitively, to create a robust logical qubit. While complicated graph-matching problems must be solved within a strict time restriction for the error decoding, several hardware implementations that satisfy the restriction at a large code distance have been proposed. However, the existing decoder designs are still challenging in reducing the logical error rate. This is because they assume that the error rates of physical qubits are uniform while they have large variations in practice. According to our numerical simulation based on the most advanced quantum chip, neglecting the non-uniform error properties of a real quantum chip in the decoding process induces significant degradation of the logical error rate and spoils the benefit of QEC. To take the non-uniformity into account, decoders need to solve matching problems on a weighted graph, but they are difficult to solve using the existing designs without exceeding the time limit of decoding. Therefore, a decoder that can treat both the non-uniform physical error rates and the large surface code is strongly demanded. In this paper, we propose a hardware design of decoding units for the surface code that can treat the non-identical error properties with small latency at a large code distance. The key idea of our design is 1) constructing a look-up table for calculating the shortest paths between nodes in a weighted graph and 2) enabling parallel processing during decoding. The implementation results in field programmable gate array (FPGA) indicate that our design scales up to code distance 11 within a microsecond-level delay, which is comparable to the existing state-of-the-art designs, while our design can treat non-identical errors.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12894105
• 書誌情報: 研究報告量子ソフトウェア（QS）; 巻 2022-QS-7, 号 16, p. 1-8, 発行日 2022-10-20
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 2435-6492
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会