Item type |
SIG Technical Reports(1) |
公開日 |
2022-09-19 |
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タイトル |
2値行列に対するパターンマイニング処理の高速化の検討 |
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言語 |
en |
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タイトル |
A Study of Pattern Mining Processing for Binary Matrices |
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言語 |
jpn |
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主題Scheme |
Other |
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主題 |
性能評価 |
資源タイプ |
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資源タイプ識別子 |
http://purl.org/coar/resource_type/c_18gh |
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資源タイプ |
technical report |
著者所属 |
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富士通株式会社 |
著者所属 |
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富士通株式会社 |
著者所属 |
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富士通株式会社 |
著者所属 |
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富士通株式会社 |
著者所属(英) |
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en |
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Fujitsu Ltd. |
著者所属(英) |
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en |
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Fujitsu Ltd. |
著者所属(英) |
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en |
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Fujitsu Ltd. |
著者所属(英) |
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en |
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Fujitsu Ltd. |
著者名 |
川上, 健太郎
栗原, 康志
山田, 芙夕楓
田原, 司睦
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論文抄録 |
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内容記述タイプ |
Other |
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内容記述 |
This paper reports on our study on speeding up the pattern mining processing for matrices whose elements are binary values of 0 or 1. For example, assume that a matrix X consisting of I rows and J columns represents the purchasing history of J persons for I products. The (i, j) component of the matrix X is set to 1 if j-th person purchased i-th product and 0 otherwise. If we want to determine whether L products are likely to be purchased by the same person, we can calculate by data mining the matrix X. The computational complexity of this processing is O(J・L・I CL), which is proportional to the L-th power of I and grows almost exponentially with L. In this paper, we examine the order of computation so that the process can be performed in realistic time for larger I, J, and L. In particular, thread parallelism and L1/L2 cache efficiency are considered. |
論文抄録(英) |
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内容記述タイプ |
Other |
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内容記述 |
This paper reports on our study on speeding up the pattern mining processing for matrices whose elements are binary values of 0 or 1. For example, assume that a matrix X consisting of I rows and J columns represents the purchasing history of J persons for I products. The (i, j) component of the matrix X is set to 1 if j-th person purchased i-th product and 0 otherwise. If we want to determine whether L products are likely to be purchased by the same person, we can calculate by data mining the matrix X. The computational complexity of this processing is O(J・L・I CL), which is proportional to the L-th power of I and grows almost exponentially with L. In this paper, we examine the order of computation so that the process can be performed in realistic time for larger I, J, and L. In particular, thread parallelism and L1/L2 cache efficiency are considered. |
書誌レコードID |
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収録物識別子タイプ |
NCID |
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収録物識別子 |
AN10463942 |
書誌情報 |
研究報告ハイパフォーマンスコンピューティング(HPC)
巻 2022-HPC-186,
号 3,
p. 1-5,
発行日 2022-09-19
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ISSN |
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収録物識別子タイプ |
ISSN |
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収録物識別子 |
2188-8841 |
Notice |
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SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc. |
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言語 |
ja |
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出版者 |
情報処理学会 |