Analysis of Performance Degradation on Shared Cache in Multicore Systems

• Item type: SIG Technical Reports(1)
• 公開日: 2020-02-20
• タイトル: Analysis of Performance Degradation on Shared Cache in Multicore Systems
• タイトル / 言語: en
• タイトル: Analysis of Performance Degradation on Shared Cache in Multicore Systems
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: ネットワーク，性能評価
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Graduate School of Informatics, Nagoya University
• 著者所属: Graduate School of Informatics, Nagoya University
• 著者所属: Graduate School of Informatics, Nagoya University
• 著者所属: Graduate School of Engineering, Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Informatics, Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Informatics, Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Informatics, Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Engineering, Nagoya University
• 著者名: Yang, Qin; Shinya, Honda; Hiroaki, Takada; Gang, Zeng
• 著者名(英): Yang, Qin; Shinya, Honda; Hiroaki, Takada; Gang, Zeng
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Modern microprocessors usually employ shard cache to keep high-speed communication with programs. Since many tasks in real-time embedded systems have implicit timing requirements, unpredictable execution time due to cache contention has become a major challenge. With carefully engineered concurrent applications, up to 168X execution time increase was observed on a real embedded multicore platform. Moreover, cache contention can cause different degrees of performance degradation concerning the characteristics of concurrent applications and processing processors. In this paper, we focus on analyzing the main factors contributing to varying performance degradations caused by the cache contention in multicore platforms. We evaluate eight SPEC 2017 benchmarks and two separate regulations doing read and write operations in memory. Evaluation results show that the application characteristics, CPU designs and implementation platforms cause significant effects on the variabilities in performance degradation.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Modern microprocessors usually employ shard cache to keep high-speed communication with programs. Since many tasks in real-time embedded systems have implicit timing requirements, unpredictable execution time due to cache contention has become a major challenge. With carefully engineered concurrent applications, up to 168X execution time increase was observed on a real embedded multicore platform. Moreover, cache contention can cause different degrees of performance degradation concerning the characteristics of concurrent applications and processing processors. In this paper, we focus on analyzing the main factors contributing to varying performance degradations caused by the cache contention in multicore platforms. We evaluate eight SPEC 2017 benchmarks and two separate regulations doing read and write operations in memory. Evaluation results show that the application characteristics, CPU designs and implementation platforms cause significant effects on the variabilities in performance degradation.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA11451459
• 書誌情報: 研究報告システムとLSIの設計技術（SLDM）; 巻 2020-SLDM-191, 号 38, p. 1-7, 発行日 2020-02-20
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 2188-8639
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会