From FLOPS to BYTES: Disruptive Change towards the Post-Moore Era (Unrefereed Workshop Manuscript)

• Item type: SIG Technical Reports(1)
• 公開日: 2016-08-01
• タイトル: From FLOPS to BYTES: Disruptive Change towards the Post-Moore Era (Unrefereed Workshop Manuscript)
• タイトル / 言語: en
• タイトル: From FLOPS to BYTES: Disruptive Change towards the Post-Moore Era (Unrefereed Workshop Manuscript)
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: HPC一般
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Global Scientific Information and Computing Center, Tokyo Institute of Technology
• 著者所属: Dept. of Information and Computer Science, Keio University
• 著者所属: Information Technology Center, The University of Tokyo
• 著者所属: Department of I&E Visionaries, Kyushu University
• 著者所属: Information Technology Center, The University of Tokyo
• 著者所属: AICS, RIKEN
• 著者所属: Dept. of Information and Communication Engineering, The University of Tokyo
• 著者所属: Information Initiative Center, Hokkaido University
• 著者所属: Information Technology Center, Nagoya University
• 著者所属: Information Technology Center, The University of Tokyo
• 著者所属: Global Scientific Information and Computing Center, Tokyo Institute of Technology
• 著者所属(英): en
• 著者所属(英): Global Scientific Information and Computing Center, Tokyo Institute of Technology
• 著者所属(英): en
• 著者所属(英): Dept. of Information and Computer Science, Keio University
• 著者所属(英): en
• 著者所属(英): Information Technology Center, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Department of I&E Visionaries, Kyushu University
• 著者所属(英): en
• 著者所属(英): Information Technology Center, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): AICS, RIKEN
• 著者所属(英): en
• 著者所属(英): Dept. of Information and Communication Engineering, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Information Initiative Center, Hokkaido University
• 著者所属(英): en
• 著者所属(英): Information Technology Center, Nagoya University
• 著者所属(英): en
• 著者所属(英): Information Technology Center, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Global Scientific Information and Computing Center, Tokyo Institute of Technology
• 著者名: Satoshi, Matsuoka; Hideharu, Amano; Kengo, Nakajima; Koji, Inoue; Tomohiro, Kudoh; Naoya, Maruyama; Kenjiro, Taura; Takeshi, Iwashita; Takahiro, Katagiri; Toshihiro, Hanawa; Toshio, Endo
• 著者名(英): Satoshi, Matsuoka; Hideharu, Amano; Kengo, Nakajima; Koji, Inoue; Tomohiro, Kudoh; Naoya, Maruyama; Kenjiro, Taura; Takeshi, Iwashita; Takahiro, Katagiri; Toshihiro, Hanawa; Toshio, Endo
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Slowdown and inevitable end in exponential scaling of processor performance, the end of the so-called “Moore's Law”is predicted to occur around 2025-2030 timeframe. Because CMOS semiconductor voltage is also approaching its limits, this means that logic transistor power will become constant, and as a result, the system FLOPS will cease to improve, resulting in serious consequences for IT in general, especially supercomputing. Existing attempts to overcome the end of Moore 's law are rather limited in their future outlook or applicability. We claim that data-oriented parameters, such as bandwidth and capacity, or BYTES, are the new parameters that will allow continued performance gains for periods even after computing performance or FLOPS ceases to improve, due to continued advances in storage device technologies and optics, and manufacturing technologies including 3-D packaging. Such transition from FLOPS to BYTES will lead to disruptive changes in the overall systems from applications, algorithms, software to architecture, as to what parameter to optimize for, in order to achieve continued performance growth over time. We are launching a new set of research efforts to investigate and devise new technologies to enable such disruptive changes from FLOPS to BYTES in the Post-Moore era, focusing on HPC, where there is extreme sensitivity to performance, and expect the results to disseminate to the rest of IT.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Slowdown and inevitable end in exponential scaling of processor performance, the end of the so-called “Moore's Law”is predicted to occur around 2025-2030 timeframe. Because CMOS semiconductor voltage is also approaching its limits, this means that logic transistor power will become constant, and as a result, the system FLOPS will cease to improve, resulting in serious consequences for IT in general, especially supercomputing. Existing attempts to overcome the end of Moore 's law are rather limited in their future outlook or applicability. We claim that data-oriented parameters, such as bandwidth and capacity, or BYTES, are the new parameters that will allow continued performance gains for periods even after computing performance or FLOPS ceases to improve, due to continued advances in storage device technologies and optics, and manufacturing technologies including 3-D packaging. Such transition from FLOPS to BYTES will lead to disruptive changes in the overall systems from applications, algorithms, software to architecture, as to what parameter to optimize for, in order to achieve continued performance growth over time. We are launching a new set of research efforts to investigate and devise new technologies to enable such disruptive changes from FLOPS to BYTES in the Post-Moore era, focusing on HPC, where there is extreme sensitivity to performance, and expect the results to disseminate to the rest of IT.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN10463942
• 書誌情報: 研究報告ハイパフォーマンスコンピューティング（HPC）; 巻 2016-HPC-155, 号 32, p. 1-14, 発行日 2016-08-01
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 2188-8841
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会