Efficient Design Exploration Framework of SW/HW Systems Based on Tightly-coupled Thread Model

• Item type: Trans(1)
• 公開日: 2015-02-12
• タイトル: Efficient Design Exploration Framework of SW/HW Systems Based on Tightly-coupled Thread Model
• タイトル / 言語: en
• タイトル: Efficient Design Exploration Framework of SW/HW Systems Based on Tightly-coupled Thread Model
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: [System-Level Design] MPSoC, TCT Model, system performance estimation, design space exploration
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Graduate School of Information Science and Technology, Osaka University
• 著者所属: Graduate School of Science and Engineering, Tokyo Institute of Technology
• 著者所属: Graduate School of Science and Engineering, Tokyo Institute of Technology
• 著者所属: Graduate School of Science and Engineering, Tokyo Institute of Technology
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology, Osaka University
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Engineering, Tokyo Institute of Technology
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Engineering, Tokyo Institute of Technology
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Engineering, Tokyo Institute of Technology
• 著者名: ArifUllahKhan; Tsuyoshi, Isshiki; Dongju, Li; Hiroaki, Kunieda
• 著者名(英): Arif, UllahKhan; Tsuyoshi, Isshiki; Dongju, Li; Hiroaki, Kunieda
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: In order to meet the increased computational requirement of today's consumer portable devices, heterogeneous multiprocessor system-on-chip (MPSoC) architectures have become widespread. These MPSoCs include not only multiple processors but also multiple dedicated hardware accelerators. Due to the increase complexity of the MPSoC, fast and accurate design space exploration (DSE) for best system performance at early stage of the design process is desired. Any DSE solution is desired to provide best system partitioning scheme for best performance with efficient area utilization. In this paper we propose a design space exploration framework for heterogeneous MPSoC based on tightly-coupled thread (TCT) parallel programing model which can handles system partition exploration and HW synthesis exploration. The proposed framework drastically reduces the exponential size design space into near-linear size by utilizing the accurate HW timing models as the indicator for system bottleneck and guiding the enumeration process of HW version combinations. Experimental results shows the accuracy of the proposed method with an average estimation error of 1.38% for HW timing of each thread, and 2.80% estimation error for the system-level simulation, where the simulation speedup factor was in the order of 5,000 times. Currently the proposed framework partially depends on a high level synthesis (HLS) tool eXCite, but other HLS tools can be easily integrated into the proposed framework.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: In order to meet the increased computational requirement of today's consumer portable devices, heterogeneous multiprocessor system-on-chip (MPSoC) architectures have become widespread. These MPSoCs include not only multiple processors but also multiple dedicated hardware accelerators. Due to the increase complexity of the MPSoC, fast and accurate design space exploration (DSE) for best system performance at early stage of the design process is desired. Any DSE solution is desired to provide best system partitioning scheme for best performance with efficient area utilization. In this paper we propose a design space exploration framework for heterogeneous MPSoC based on tightly-coupled thread (TCT) parallel programing model which can handles system partition exploration and HW synthesis exploration. The proposed framework drastically reduces the exponential size design space into near-linear size by utilizing the accurate HW timing models as the indicator for system bottleneck and guiding the enumeration process of HW version combinations. Experimental results shows the accuracy of the proposed method with an average estimation error of 1.38% for HW timing of each thread, and 2.80% estimation error for the system-level simulation, where the simulation speedup factor was in the order of 5,000 times. Currently the proposed framework partially depends on a high level synthesis (HLS) tool eXCite, but other HLS tools can be easily integrated into the proposed framework.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 8, p. 38-50, 発行日 2015-02-12
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会