A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures

• Item type: Trans(1)
• 公開日: 2014-08-04
• タイトル: A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures
• タイトル / 言語: en
• タイトル: A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: [Behavioral Synthesis] process and delay variation, post-silicon tuning, high-level synthesis, distributed-register architecture
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Department of Computer Science and Engineering, Waseda University
• 著者所属: Department of Electronic and Photonic Systems, Waseda University
• 著者所属: Department of Computer Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Electronic and Photonic Systems, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science and Engineering, Waseda University
• 著者名: Yuta, Hagio; Masao, Yanagisawa; Nozomu, Togawa
• 著者名(英): Yuta, Hagio; Masao, Yanagisawa; Nozomu, Togawa
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: As device feature size drops, interconnection delays often exceed gate delays. We have to incorporate interconnection delays even in high-level synthesis. Using RDR architectures is one of the effective solutions to this problem. At the same time, process and delay variation also becomes a serious problem which may result in several timing errors. How to deal with this problem is another key issue in high-level synthesis. In this paper, we propose a delay-variation-aware high-level synthesis algorithm for RDR architectures. We first obtain a non-delayed scheduling/binding result and, based on it, we also obtain a delayed scheduling/binding result. By adding several extra functional units to vacant RDR islands, we can have a delayed scheduling/binding result so that its latency is not much increased compared with the non-delayed one. After that, we similarize the two scheduling/binding results by repeatedly modifying their results. We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: As device feature size drops, interconnection delays often exceed gate delays. We have to incorporate interconnection delays even in high-level synthesis. Using RDR architectures is one of the effective solutions to this problem. At the same time, process and delay variation also becomes a serious problem which may result in several timing errors. How to deal with this problem is another key issue in high-level synthesis. In this paper, we propose a delay-variation-aware high-level synthesis algorithm for RDR architectures. We first obtain a non-delayed scheduling/binding result and, based on it, we also obtain a delayed scheduling/binding result. By adding several extra functional units to vacant RDR islands, we can have a delayed scheduling/binding result so that its latency is not much increased compared with the non-delayed one. After that, we similarize the two scheduling/binding results by repeatedly modifying their results. We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 7, p. 81-90, 発行日 2014-08-04
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会