Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework

• Item type: Trans(1)
• 公開日: 2012-08-06
• タイトル: Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework
• タイトル / 言語: en
• タイトル: Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: [System-Level Energy Optimization] energy optimization, embedded real-time system, dynamic energy performance scaling
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Graduate School of Information Science, Nagoya University
• 著者所属: Graduate School of Engineering, Nagoya University
• 著者所属: Graduate School of Information Science, Nagoya University／Presently with Graduate School of Informatics
• 著者所属: Graduate School of Information Science, Nagoya University
• 著者所属: Graduate School of Information Science, Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Engineering, Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University / Presently with Graduate School of Informatics
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nagoya University
• 著者名: Hirotaka, Kawashima; Gang, Zeng; Hideki, Takase; Masato, Edahiro; Hiroaki, Takada
• 著者名(英): Hirotaka, Kawashima; Gang, Zeng; Hideki, Takase; Masato, Edahiro; Hiroaki, Takada
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: A dynamic energy performance scaling (DEPS) framework has been proposed as a generalization of dynamic voltage frequency scaling (DVFS). The DEPS framework selects an energy-optimal hardware configuration at runtime. To reduce runtime overhead, Pareto-optimal combinations of hardware configurations should be provided via DEPS profiling during the design phase. The challenge of DEPS profiling lies in extracting the Pareto-optimal combinations efficiently from the exponential search space. We propose two exact algorithms to reduce the number of calculations in DEPS profiling. These algorithms can be used with common search algorithms. We also propose a heuristic algorithm for searching Pareto-optimal configurations efficiently. Extensive experiments are performed, and they demonstrate that the proposed algorithms can complete DEPS profiling within a reasonable amount of time and generate optimal DEPS profiles. It is believed that the proposed algorithms will enable easy application of the DEPS framework in practice.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: A dynamic energy performance scaling (DEPS) framework has been proposed as a generalization of dynamic voltage frequency scaling (DVFS). The DEPS framework selects an energy-optimal hardware configuration at runtime. To reduce runtime overhead, Pareto-optimal combinations of hardware configurations should be provided via DEPS profiling during the design phase. The challenge of DEPS profiling lies in extracting the Pareto-optimal combinations efficiently from the exponential search space. We propose two exact algorithms to reduce the number of calculations in DEPS profiling. These algorithms can be used with common search algorithms. We also propose a heuristic algorithm for searching Pareto-optimal configurations efficiently. Extensive experiments are performed, and they demonstrate that the proposed algorithms can complete DEPS profiling within a reasonable amount of time and generate optimal DEPS profiles. It is believed that the proposed algorithms will enable easy application of the DEPS framework in practice.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology（TSLDM）; 巻 5, p. 133-142, 発行日 2012-08-06
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会