CBM: Core Based Memory Scheduling method

• Item type: SIG Technical Reports(1)
• 公開日: 2012-07-25
• タイトル: CBM: Core Based Memory Scheduling method
• タイトル / 言語: en
• タイトル: CBM: Core Based Memory Scheduling method
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: 高速化手法
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: The university of Tokyo
• 著者所属: The university of Tokyo／NEC
• 著者所属: The university of Tokyo
• 著者所属: The university of Tokyo
• 著者所属(英): en
• 著者所属(英): The university of Tokyo
• 著者所属(英): en
• 著者所属(英): The university of Tokyo / NEC
• 著者所属(英): en
• 著者所属(英): The university of Tokyo
• 著者所属(英): en
• 著者所属(英): The university of Tokyo
• 著者名: Kohei, Hosokawa; Yasuo, Ishii; Mary, Inaba; Kei, Hiraki
• 著者名(英): Kohei, Hosokawa; Yasuo, Ishii; Mary, Inaba; Kei, Hiraki
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: In modern chip-multiprocessor systems，DRAM is shared among multiple threads．The memory scheduler must resolve the inter-thread contention for the DRAM effectiveness．Previously proposed DRAM memory schedulers have calculated the memory access intensity of each thread for the priority scheduling．Existing methods [2]，[3] analyze the number of memory requests served in memory controller to get memory-intensity，but these methods lack prediction accuracy．TCM [1] avoids this problem by using MPKI information．TCM can improve the prediction accuracy，but takes very long cycles to update the thread priority．As a result, TCM lacks the timeliness of the priority prediction．This paper presents a new memory scheduling method，Core-Based Memory scheduling (CBM)，which utilizes core information for memory-intensity evaluation of each thread. Our key idea is 1) to refer the distance of instruction count between each memory request for the priority calculation, and 2) to place the priority scheduler on each core．CBM judges the core calculation progress by comparing the instruction counter distance between the new memory request and the last one．By doing so，CBM can utilize the instruction progress information of each core directly，thus we can predict the memory-intensity more accurately．CBM also proposes to calculate the thread priority not on the memory controller but on the private cache of each core．By doing so, even in concurrent many-channel memory system，CBM can decide priority without the heavy inter-channel communication．Therefore, CBM accomplishes high timeliness on the priority update．We evaluate CBM by using the workloads of Memory Scheduling Championship (MSC) and compare its performance to two existing scheduling algorithms. We found that CBM achieves both the best throughput and fairness．
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: In modern chip-multiprocessor systems，DRAM is shared among multiple threads．The memory scheduler must resolve the inter-thread contention for the DRAM effectiveness．Previously proposed DRAM memory schedulers have calculated the memory access intensity of each thread for the priority scheduling．Existing methods [2]，[3] analyze the number of memory requests served in memory controller to get memory-intensity，but these methods lack prediction accuracy．TCM [1] avoids this problem by using MPKI information．TCM can improve the prediction accuracy，but takes very long cycles to update the thread priority．As a result, TCM lacks the timeliness of the priority prediction．This paper presents a new memory scheduling method，Core-Based Memory scheduling (CBM)，which utilizes core information for memory-intensity evaluation of each thread. Our key idea is 1) to refer the distance of instruction count between each memory request for the priority calculation, and 2) to place the priority scheduler on each core．CBM judges the core calculation progress by comparing the instruction counter distance between the new memory request and the last one．By doing so，CBM can utilize the instruction progress information of each core directly，thus we can predict the memory-intensity more accurately．CBM also proposes to calculate the thread priority not on the memory controller but on the private cache of each core．By doing so, even in concurrent many-channel memory system，CBM can decide priority without the heavy inter-channel communication．Therefore, CBM accomplishes high timeliness on the priority update．We evaluate CBM by using the workloads of Memory Scheduling Championship (MSC) and compare its performance to two existing scheduling algorithms. We found that CBM achieves both the best throughput and fairness．
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN10096105
• 書誌情報: 研究報告計算機アーキテクチャ（ARC）; 巻 2012-ARC-201, 号 9, p. 1-6, 発行日 2012-07-25
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会