0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme

• Item type: Trans(1)
• 公開日: 2012-02-21
• タイトル: 0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme
• タイトル / 言語: en
• タイトル: 0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: Architectural Design
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Graduate School of System Informatics, Kobe University
• 著者所属: Graduate School of System Informatics, Kobe University
• 著者所属: Graduate School of System Informatics, Kobe University
• 著者所属: Graduate School of System Informatics, Kobe University／JST CREST
• 著者所属(英): en
• 著者所属(英): Graduate School of System Informatics, Kobe University
• 著者所属(英): en
• 著者所属(英): Graduate School of System Informatics, Kobe University
• 著者所属(英): en
• 著者所属(英): Graduate School of System Informatics, Kobe University
• 著者所属(英): en
• 著者所属(英): Graduate School of System Informatics, Kobe University / JST CREST
• 著者名: Yohei, Nakata; Shunsuke, Okumura; Hiroshi, Kawaguchi; Masahiko, Yoshimoto
• 著者名(英): Yohei, Nakata; Shunsuke, Okumura; Hiroshi, Kawaguchi; Masahiko, Yoshimoto
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: This paper presents a novel cache architecture using 7T/14T SRAM, which can improve its reliability with control lines dynamically. Our proposed 14T word-enhancing scheme can enhance its operating margin in word granularity by combining two words in a low-voltage mode. Furthermore, we propose a new testing method that maximizes the efficiency of the 14T word-enhancing scheme. In a 65-nm process, it can reduce the minimum operation voltage (Vmin) to 0.5V to a level that is 42% and 21% lower, respectively, than those of a conventional 6T SRAM and a cache word-disable scheme. Measurement results show that the 14T word-enhancing scheme can reduce Vmin of the 6T SRAM and 14T dependable modes by 25% and 19%, respectively. The respective dynamic power reductions are 89.2% and 73.9%. The respective total power reductions are 44.8% and 20.9%.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: This paper presents a novel cache architecture using 7T/14T SRAM, which can improve its reliability with control lines dynamically. Our proposed 14T word-enhancing scheme can enhance its operating margin in word granularity by combining two words in a low-voltage mode. Furthermore, we propose a new testing method that maximizes the efficiency of the 14T word-enhancing scheme. In a 65-nm process, it can reduce the minimum operation voltage (Vmin) to 0.5V to a level that is 42% and 21% lower, respectively, than those of a conventional 6T SRAM and a cache word-disable scheme. Measurement results show that the 14T word-enhancing scheme can reduce Vmin of the 6T SRAM and 14T dependable modes by 25% and 19%, respectively. The respective dynamic power reductions are 89.2% and 73.9%. The respective total power reductions are 44.8% and 20.9%.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology（TSLDM）; 巻 5, p. 32-43, 発行日 2012-02-21
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会