{"created":"2025-01-18T23:35:40.415723+00:00","updated":"2025-01-21T19:20:34.212979+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00081497","sets":["934:1160:6745"]},"path":["6745"],"owner":"11","recid":"81497","title":["0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme"],"pubdate":{"attribute_name":"公開日","attribute_value":"2012-02-21"},"_buckets":{"deposit":"1cffce8b-9ce8-4db7-84e0-d44491bc9aa6"},"_deposit":{"id":"81497","pid":{"type":"depid","value":"81497","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme"},{"subitem_title":"0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Architectural Design","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2012-02-21","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Graduate School of System Informatics, Kobe University"},{"subitem_text_value":"Graduate School of System Informatics, Kobe University"},{"subitem_text_value":"Graduate School of System Informatics, Kobe University"},{"subitem_text_value":"Graduate School of System Informatics, Kobe University／JST CREST"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of System Informatics, Kobe University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of System Informatics, Kobe University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of System Informatics, Kobe University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of System Informatics, Kobe University / JST CREST","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/81497/files/IPSJ-TSLDM0500005.pdf"},"date":[{"dateType":"Available","dateValue":"2014-02-21"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0500005.pdf","filesize":[{"value":"2.4 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"742e7726-d9fc-4cf2-b238-ddcf57648b6f","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2012 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yohei, Nakata"},{"creatorName":"Shunsuke, Okumura"},{"creatorName":"Hiroshi, Kawaguchi"},{"creatorName":"Masahiko, Yoshimoto"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yohei, Nakata","creatorNameLang":"en"},{"creatorName":"Shunsuke, Okumura","creatorNameLang":"en"},{"creatorName":"Hiroshi, Kawaguchi","creatorNameLang":"en"},{"creatorName":"Masahiko, Yoshimoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12394951","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6687","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"This paper presents a novel cache architecture using 7T/14T SRAM, which can improve its reliability with control lines dynamically. Our proposed 14T word-enhancing scheme can enhance its operating margin in word granularity by combining two words in a low-voltage mode. Furthermore, we propose a new testing method that maximizes the efficiency of the 14T word-enhancing scheme. In a 65-nm process, it can reduce the minimum operation voltage (Vmin) to 0.5V to a level that is 42% and 21% lower, respectively, than those of a conventional 6T SRAM and a cache word-disable scheme. Measurement results show that the 14T word-enhancing scheme can reduce Vmin of the 6T SRAM and 14T dependable modes by 25% and 19%, respectively. The respective dynamic power reductions are 89.2% and 73.9%. The respective total power reductions are 44.8% and 20.9%.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper presents a novel cache architecture using 7T/14T SRAM, which can improve its reliability with control lines dynamically. Our proposed 14T word-enhancing scheme can enhance its operating margin in word granularity by combining two words in a low-voltage mode. Furthermore, we propose a new testing method that maximizes the efficiency of the 14T word-enhancing scheme. In a 65-nm process, it can reduce the minimum operation voltage (Vmin) to 0.5V to a level that is 42% and 21% lower, respectively, than those of a conventional 6T SRAM and a cache word-disable scheme. Measurement results show that the 14T word-enhancing scheme can reduce Vmin of the 6T SRAM and 14T dependable modes by 25% and 19%, respectively. The respective dynamic power reductions are 89.2% and 73.9%. The respective total power reductions are 44.8% and 20.9%.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"43","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology（TSLDM）"}],"bibliographicPageStart":"32","bibliographicIssueDates":{"bibliographicIssueDate":"2012-02-21","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"5"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":81497,"links":{}}