32-bit Microprocessors Based on the TRON Architecture Specification

• Item type: JInfP(1)
• 公開日: 1990-08-25
• タイトル: 32-bit Microprocessors Based on the TRON Architecture Specification
• タイトル / 言語: en
• タイトル: 32-bit Microprocessors Based on the TRON Architecture Specification
• 言語: eng
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Department of Information Science Faculty of Science University of Tokyo
• 著者所属: Advanced Microprocessor Development Dept LSI R&D Lab. Mitsubishi Electric Corporation
• 著者所属(英): en
• 著者所属(英): Department of Information Science, Faculty of Science, University of Tokyo
• 著者所属(英): en
• 著者所属(英): Advanced Microprocessor Development Dept, LSI R&D Lab., Mitsubishi Electric Corporation
• 著者名: Ken, Sakamura; Tatsuya, Enomoto
• 著者名(英): Ken, Sakamura; Tatsuya, Enomoto
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Various general-purpose 32-bit microprocessors are being designed and manufactured on the basis of the TRON (the realtime operating system nucleus) specification developed in a TRON subproject. These chips which will utilize advanced VLSI technologies of the 1990's to the limit are to be optimized for operating systems based on TRON specifications developed in other TRON subprojects and will act as a powerful engine for the entire TRON project. The chip architecture of the TRON specification has been designed as part of the total architecture in parallel with the design of the TRON specifications for operating systems. Anyone is and will be allowed to develop new microprocessors freely and independently on the basis of suggested external specifications. This open architecture constitutes an epoch-making advance over existing microprocessor architectures. Although there are a number of general-purpose 32-bit microprocessors already on the market the chip architecture of the TRON specification has been newly designed from scratch and several semiconductor manufacturers are now developing microprocessors with the new architecture. It should be noted that the development of these chips has been triggered by a recognition that a new architecture will be required to match the fields in which microprocessors will be applied in the 1990's; one that will allow the most advanced VLSI technology to be fully implemented rather than one bound by the need for compatibility with existing architectures. The first half of this paper gives a brief overview of the TRON project the design philosophy of the TRON specification for the VLSI CPU and the chip architecture of the TRON specification in Sections 2 3 and 4 respectively. The second half describes the technologies involved in its realization and examples of products. In Section 5 VLSI implementation based on the TRON architecture specification is described in the case of the GMlcRo/1OO. Since related development tools and operating systems are necessary for a microprocessor with a new architecture to have practical applications these will be mentioned in addition to related VLSIs. Results of the evaluation of the G_MICRO/ 100 and related development tools are also described in Section 5. An ex-ample of an implementation of a realtime operating system running on the G_MICRO/1OO and based on the ITRON specification is described in Section 6 in order to show that the TRON architecture is designed as a total architecture.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Various general-purpose 32-bit microprocessors are being designed and manufactured on the basis of the TRON (the realtime operating system nucleus) specification developed in a TRON subproject. These chips, which will utilize advanced VLSI technologies of the 1990's to the limit, are to be optimized for operating systems based on TRON specifications developed in other TRON subprojects, and will act as a powerful engine for the entire TRON project. The chip architecture of the TRON specification has been designed as part of the total architecture, in parallel with the design of the TRON specifications for operating systems. Anyone is and will be allowed to develop new microprocessors freely and independently on the basis of suggested external specifications. This open architecture constitutes an epoch-making advance over existing microprocessor architectures. Although there are a number of general-purpose 32-bit microprocessors already on the market, the chip architecture of the TRON specification has been newly designed from scratch, and several semiconductor manufacturers are now developing microprocessors with the new architecture. It should be noted that the development of these chips has been triggered by a recognition that a new architecture will be required to match the fields in which microprocessors will be applied in the 1990's; one that will allow the most advanced VLSI technology to be fully implemented, rather than one bound by the need for compatibility with existing architectures. The first half of this paper gives a brief overview of the TRON project, the design philosophy of the TRON specification for the VLSI CPU, and the chip architecture of the TRON specification, in Sections 2, 3, and 4,respectively. The second half describes the technologies involved in its realization and examples of products. In Section 5, VLSI implementation based on the TRON architecture specification is described in the case of the GMlcRo/1OO. Since related development tools and operating systems are necessary for a microprocessor with a new architecture to have practical applications, these will be mentioned in addition to related VLSIs. Results of the evaluation of the G_MICRO/ 100 and related development tools are also described in Section 5. An ex-ample of an implementation of a realtime operating system running on the G_MICRO/1OO and based on the ITRON specification is described in Section 6 in order to show that the TRON architecture is designed as a total architecture.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA00700121
• 書誌情報: Journal of Information Processing; 巻 13, 号 2, p. 130-143, 発行日 1990-08-25
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6652
• 出版者 / 言語: ja
• 出版者: 情報処理学会