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画像処理プロセッサTIP - 3ハードウェア構成
https://ipsj.ixsq.nii.ac.jp/records/53783
https://ipsj.ixsq.nii.ac.jp/records/53783421d23bf-f45a-41eb-9e21-987b7199a88e
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
IPSJ-CVIM84032001.pdf (977.5 kB)
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Copyright (c) 1984 by the Information Processing Society of Japan
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| オープンアクセス | ||
| Item type | SIG Technical Reports(1) | |||||||
|---|---|---|---|---|---|---|---|---|
| 公開日 | 1984-09-20 | |||||||
| タイトル | ||||||||
| タイトル | 画像処理プロセッサTIP - 3ハードウェア構成 | |||||||
| タイトル | ||||||||
| 言語 | en | |||||||
| タイトル | An Image Processor TIP - 3 Hardware Configuration | |||||||
| 言語 | ||||||||
| 言語 | jpn | |||||||
| 資源タイプ | ||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_18gh | |||||||
| 資源タイプ | technical report | |||||||
| 著者所属 | ||||||||
| 日本電気（株）C&Cシステム研究所 | ||||||||
| 著者所属 | ||||||||
| 日本電気（株）C&Cシステム研究所 | ||||||||
| 著者所属 | ||||||||
| 日本電気（株）C&Cシステム研究所 | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| C&C Systems Res. Labs. NEC Corporation | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| C&C Systems Res. Labs. NEC Corporation | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| C&C Systems Res. Labs. NEC Corporation | ||||||||
| 著者名 |
森下, 丈
× 森下, 丈
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| 著者名(英) |
Takeshi, Morishita
× Takeshi, Morishita
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| 論文抄録 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | A chip-oriented data-flow image processor TIP-3 is proposed and its hardware configuration is described. TIP-3 aims at a compact cost-effective and high speed image processing system in an interactive evironment. TIP-3 onsists of four units; a Process Support Unit (PSU) an Image Processing Unit (IPU) a Display Control Unit (DCU) and an Image Memory (IM). The IPU is a ring-shaped multiple processor array which includes 8 ImPPs (Image Pipelined Processor) and a MAGIC (Memory Access and General bus Interface Chip) and performs flexibly programable pipeline operation. A data-driven control mechanism is applied to both software and hardware. IPU's processing capabilities are estimated by computer simulation. | |||||||
| 論文抄録(英) | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | A chip-oriented data-flow image processor TIP-3 is proposed and its hardware configuration is described. TIP-3 aims at a compact, cost-effective and high speed image processing system in an interactive evironment. TIP-3 onsists of four units; a Process Support Unit (PSU), an Image Processing Unit (IPU), a Display Control Unit (DCU) and an Image Memory (IM). The IPU is a ring-shaped multiple processor array which includes 8 ImPPs (Image Pipelined Processor) and a MAGIC (Memory Access and General bus Interface Chip) and performs flexibly programable pipeline operation. A data-driven control mechanism is applied to both software and hardware. IPU's processing capabilities are estimated by computer simulation. | |||||||
| 書誌レコードID | ||||||||
| 収録物識別子タイプ | NCID | |||||||
| 収録物識別子 | AA11131797 | |||||||
| 書誌情報 |
情報処理学会研究報告コンピュータビジョンとイメージメディア（CVIM） 巻 1984, 号 34(1984-CVIM-032), p. 1-8, 発行日 1984-09-20 |
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| Notice | ||||||||
| SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc. | ||||||||
| 出版者 | ||||||||
| 言語 | ja | |||||||
| 出版者 | 情報処理学会 | |||||||
