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Hierarchical Matrix Calculation for FPGA using SYCL
https://ipsj.ixsq.nii.ac.jp/records/231073
https://ipsj.ixsq.nii.ac.jp/records/231073be221c69-161c-4a7d-8639-ffb12b9fc73f
| 名前 / ファイル | ライセンス | アクション |
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IPSJ-ARC23255034.pdf (1.9 MB)
2025年11月28日からダウンロード可能です。
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Copyright (c) 2023 by the Information Processing Society of Japan
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| 非会員：¥660, IPSJ:学会員：¥330, ARC:会員：¥0, DLIB:会員：¥0 | ||
| Item type | SIG Technical Reports(1) | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 公開日 | 2023-11-28 | |||||||||
| タイトル | ||||||||||
| タイトル | Hierarchical Matrix Calculation for FPGA using SYCL | |||||||||
| タイトル | ||||||||||
| 言語 | en | |||||||||
| タイトル | Hierarchical Matrix Calculation for FPGA using SYCL | |||||||||
| 言語 | ||||||||||
| 言語 | eng | |||||||||
| キーワード | ||||||||||
| 主題Scheme | Other | |||||||||
| 主題 | アクセラレータ | |||||||||
| 資源タイプ | ||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_18gh | |||||||||
| 資源タイプ | technical report | |||||||||
| 著者所属 | ||||||||||
| The University of Tokyo | ||||||||||
| 著者所属 | ||||||||||
| The University of Tokyo | ||||||||||
| 著者所属(英) | ||||||||||
| en | ||||||||||
| The University of Tokyo | ||||||||||
| 著者所属(英) | ||||||||||
| en | ||||||||||
| The University of Tokyo | ||||||||||
| 著者名 |
Yijie, Yu
× Yijie, Yu
× Toshihiro, Hanawa
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| 著者名(英) |
Yijie, Yu
× Yijie, Yu
× Toshihiro, Hanawa
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| 論文抄録 | ||||||||||
| 内容記述タイプ | Other | |||||||||
| 内容記述 | In recent years, Field Programmable Gate Arrays (FPGAs) have been studied as a new accelerator of the HPC field since it enables custom hardware for application-specific functions. Compared to conventional OpenCL descriptions, SYCL simplifies managing codes because it does not require the separation of host and device code. We designed and optimized a computation kernel of HACApK, a hierarchical matrix library (H-matrix), using SYCL for the FPGA acceleration. H-matrix can reduce computation and memory usage by approximating submatrices of dense matrices with low-rank matrices and representing the original large dense matrix as a set of smaller dense matrices and low-rank approximation matrices and are considered suitable for FPGA implementation because of their relatively complex calculation patterns that mix dense and low-rank approximation matrices. In this study, the matrix-vector multiplication in HACApK was ported to SYCL and optimized using several techniques. As a result, almost the same performance as the single CPU core of the Intel Xeon Skylake could be achieved with the single pipeline. | |||||||||
| 論文抄録(英) | ||||||||||
| 内容記述タイプ | Other | |||||||||
| 内容記述 | In recent years, Field Programmable Gate Arrays (FPGAs) have been studied as a new accelerator of the HPC field since it enables custom hardware for application-specific functions. Compared to conventional OpenCL descriptions, SYCL simplifies managing codes because it does not require the separation of host and device code. We designed and optimized a computation kernel of HACApK, a hierarchical matrix library (H-matrix), using SYCL for the FPGA acceleration. H-matrix can reduce computation and memory usage by approximating submatrices of dense matrices with low-rank matrices and representing the original large dense matrix as a set of smaller dense matrices and low-rank approximation matrices and are considered suitable for FPGA implementation because of their relatively complex calculation patterns that mix dense and low-rank approximation matrices. In this study, the matrix-vector multiplication in HACApK was ported to SYCL and optimized using several techniques. As a result, almost the same performance as the single CPU core of the Intel Xeon Skylake could be achieved with the single pipeline. | |||||||||
| 書誌レコードID | ||||||||||
| 収録物識別子タイプ | NCID | |||||||||
| 収録物識別子 | AN10096105 | |||||||||
| 書誌情報 |
研究報告システム・アーキテクチャ（ARC） 巻 2023-ARC-255, 号 34, p. 1-7, 発行日 2023-11-28 |
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| ISSN | ||||||||||
| 収録物識別子タイプ | ISSN | |||||||||
| 収録物識別子 | 2188-8574 | |||||||||
| Notice | ||||||||||
| SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc. | ||||||||||
| 出版者 | ||||||||||
| 言語 | ja | |||||||||
| 出版者 | 情報処理学会 | |||||||||
