{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00231073","sets":["1164:1579:11081:11407"]},"path":["11407"],"owner":"44499","recid":"231073","title":["Hierarchical Matrix Calculation for FPGA using SYCL"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-11-28"},"_buckets":{"deposit":"79fde780-70c0-428b-96d8-2e18f5ef50ef"},"_deposit":{"id":"231073","pid":{"type":"depid","value":"231073","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"Hierarchical Matrix Calculation for FPGA using SYCL","author_link":["623247","623246","623249","623248"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Hierarchical Matrix Calculation for FPGA using SYCL"},{"subitem_title":"Hierarchical Matrix Calculation for FPGA using SYCL","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"アクセラレータ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-11-28","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"The University of Tokyo"},{"subitem_text_value":"The University of Tokyo"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/231073/files/IPSJ-ARC23255034.pdf","label":"IPSJ-ARC23255034.pdf"},"date":[{"dateType":"Available","dateValue":"2025-11-28"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC23255034.pdf","filesize":[{"value":"1.9 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"615cd940-9966-440f-b72e-6e6e56de5605","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yijie, Yu"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Toshihiro, Hanawa"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yijie, Yu","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Toshihiro, Hanawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"In recent years, Field Programmable Gate Arrays (FPGAs) have been studied as a new accelerator of the HPC field since it enables custom hardware for application-specific functions. Compared to conventional OpenCL descriptions, SYCL simplifies managing codes because it does not require the separation of host and device code. We designed and optimized a computation kernel of HACApK, a hierarchical matrix library (H-matrix), using SYCL for the FPGA acceleration. H-matrix can reduce computation and memory usage by approximating submatrices of dense matrices with low-rank matrices and representing the original large dense matrix as a set of smaller dense matrices and low-rank approximation matrices and are considered suitable for FPGA implementation because of their relatively complex calculation patterns that mix dense and low-rank approximation matrices. In this study, the matrix-vector multiplication in HACApK was ported to SYCL and optimized using several techniques. As a result, almost the same performance as the single CPU core of the Intel Xeon Skylake could be achieved with the single pipeline.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In recent years, Field Programmable Gate Arrays (FPGAs) have been studied as a new accelerator of the HPC field since it enables custom hardware for application-specific functions. Compared to conventional OpenCL descriptions, SYCL simplifies managing codes because it does not require the separation of host and device code. We designed and optimized a computation kernel of HACApK, a hierarchical matrix library (H-matrix), using SYCL for the FPGA acceleration. H-matrix can reduce computation and memory usage by approximating submatrices of dense matrices with low-rank matrices and representing the original large dense matrix as a set of smaller dense matrices and low-rank approximation matrices and are considered suitable for FPGA implementation because of their relatively complex calculation patterns that mix dense and low-rank approximation matrices. In this study, the matrix-vector multiplication in HACApK was ported to SYCL and optimized using several techniques. As a result, almost the same performance as the single CPU core of the Intel Xeon Skylake could be achieved with the single pipeline.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"7","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-11-28","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"34","bibliographicVolumeNumber":"2023-ARC-255"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:31:13.094955+00:00","updated":"2025-01-19T10:53:12.980772+00:00","id":231073}