Initial Design and Evaluation of Riken CGRA: Data-Driven Architecture for Future HPC

• Item type: SIG Technical Reports(1)
• 公開日: 2022-01-17
• タイトル: Initial Design and Evaluation of Riken CGRA: Data-Driven Architecture for Future HPC
• タイトル / 言語: en
• タイトル: Initial Design and Evaluation of Riken CGRA: Data-Driven Architecture for Future HPC
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: HPC
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Riken Center for Computational Science
• 著者所属: Riken Center for Computational Science
• 著者所属: Riken Center for Computational Science
• 著者所属: Riken Center for Computational Science / Graduate School of Information Science and Technology, The University of Tokyo
• 著者所属: KTH Royal Institute of Technology
• 著者所属: Riken Center for Computational Science
• 著者所属(英): en
• 著者所属(英): Riken Center for Computational Science
• 著者所属(英): en
• 著者所属(英): Riken Center for Computational Science
• 著者所属(英): en
• 著者所属(英): Riken Center for Computational Science
• 著者所属(英): en
• 著者所属(英): Riken Center for Computational Science / Graduate School of Information Science and Technology, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): KTH Royal Institute of Technology
• 著者所属(英): en
• 著者所属(英): Riken Center for Computational Science
• 著者名: Boma, Adhi; Carlos, Cortes; Yiyu, Tan; Takuya, Kojima; Artur, Podabas; Kentaro, Sano
• 著者名(英): Boma, Adhi; Carlos, Cortes; Yiyu, Tan; Takuya, Kojima; Artur, Podabas; Kentaro, Sano
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: We require different processor architectures from the present mainstream of many-core CPU architecture to further scale the computing performance at an acceptable power efficiency in the forthcoming Post-Moore era. The Coarse-Grained Reconfigurable Array (CGRA) is a promising architecture to overcome scaling limitations of the current many-core architecture, especially for spatially expanded data-flow graphs of operations that can be fully pipelined, be locally controlled, and benefit from specialization for target problems with efficient data movement. This report introduces our research project on CGRA for future HPC, from its concept, initial design, toolchain, and preliminary verification to the performance evaluation results with RTL simulation.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: We require different processor architectures from the present mainstream of many-core CPU architecture to further scale the computing performance at an acceptable power efficiency in the forthcoming Post-Moore era. The Coarse-Grained Reconfigurable Array (CGRA) is a promising architecture to overcome scaling limitations of the current many-core architecture, especially for spatially expanded data-flow graphs of operations that can be fully pipelined, be locally controlled, and benefit from specialization for target problems with efficient data movement. This report introduces our research project on CGRA for future HPC, from its concept, initial design, toolchain, and preliminary verification to the performance evaluation results with RTL simulation.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN10096105
• 書誌情報: 研究報告システム・アーキテクチャ（ARC）; 巻 2022-ARC-247, 号 25, p. 1-6, 発行日 2022-01-17
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 2188-8574
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会