{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00216112","sets":["1164:1579:10818:10819"]},"path":["10819"],"owner":"44499","recid":"216112","title":["Initial Design and Evaluation of Riken CGRA: Data-Driven Architecture for Future HPC"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-01-17"},"_buckets":{"deposit":"a2dd0a8d-4f4c-477e-b40a-20edf7f35a9e"},"_deposit":{"id":"216112","pid":{"type":"depid","value":"216112","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"Initial Design and Evaluation of Riken CGRA: Data-Driven Architecture for Future HPC","author_link":["557501","557494","557499","557500","557491","557495","557497","557492","557493","557496","557502","557498"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Initial Design and Evaluation of Riken CGRA: Data-Driven Architecture for Future HPC"},{"subitem_title":"Initial Design and Evaluation of Riken CGRA: Data-Driven Architecture for Future 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acceptable power efficiency in the forthcoming Post-Moore era. The Coarse-Grained Reconfigurable Array (CGRA) is a promising architecture to overcome scaling limitations of the current many-core architecture, especially for spatially expanded data-flow graphs of operations that can be fully pipelined, be locally controlled, and benefit from specialization for target problems with efficient data movement. This report introduces our research project on CGRA for future HPC, from its concept, initial design, toolchain, and preliminary verification to the performance evaluation results with RTL simulation.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"We require different processor architectures from the present mainstream of many-core CPU architecture to further scale the computing performance at an acceptable power efficiency in the forthcoming Post-Moore era. The Coarse-Grained Reconfigurable Array (CGRA) is a promising architecture to overcome scaling limitations of the current many-core architecture, especially for spatially expanded data-flow graphs of operations that can be fully pipelined, be locally controlled, and benefit from specialization for target problems with efficient data movement. This report introduces our research project on CGRA for future HPC, from its concept, initial design, toolchain, and preliminary verification to the performance evaluation results with RTL simulation.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-01-17","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"25","bibliographicVolumeNumber":"2022-ARC-247"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":216112,"updated":"2025-01-19T15:55:49.020023+00:00","links":{},"created":"2025-01-19T01:16:50.200401+00:00"}