FPGA Based Accelerator for Neural Networks Computation with Flexible Pipelining

• Item type: SIG Technical Reports(1)
• 公開日: 2021-11-24
• タイトル: FPGA Based Accelerator for Neural Networks Computation with Flexible Pipelining
• タイトル / 言語: en
• タイトル: FPGA Based Accelerator for Neural Networks Computation with Flexible Pipelining
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: 設計事例
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Graduate School of Engineering, The University of Tokyo
• 著者所属: Waseda Research Institute for Science and Engineering, Waseda University／JST, PRESTO
• 著者所属: System Design Research Center, University of Tokyo
• 著者所属(英): en
• 著者所属(英): Graduate School of Engineering, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Waseda Research Institute for Science and Engineering, Waseda University / JST, PRESTO
• 著者所属(英): en
• 著者所属(英): System Design Research Center, University of Tokyo
• 著者名: Qingyang, Yi; Heming, Sun; Masahiro, Fujita
• 著者名(英): Qingyang, Yi; Heming, Sun; Masahiro, Fujita
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: FPGA is appropriate for fix-point neural networks computing due to high power efficiency and configurability. However, its design must be intensively refined to achieve high performance using limited hardware resources. We present an FPGA-based neural networks accelerator and its optimization framework, which can achieve optimal efficiency for various CNN models and FPGA resources. Targeting high throughput, we adopt layer-wise pipeline architecture for higher DSP utilization. To get the optimal performance, a flexible algorithm to allocate balanced hardware resources to each layer is also proposed, supported by activation buffer design. Through our well-balanced implementation of four CNN models on ZC706, the DSP utilization and efficiency are over 90%. For VGG16 on ZC706, the proposed accelerator achieves the performance of 2.58x, 1.53x and 1.35x better than the referenced non-pipeline architecture [1], pipeline architecture [2] and [3], respectively.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: FPGA is appropriate for fix-point neural networks computing due to high power efficiency and configurability. However, its design must be intensively refined to achieve high performance using limited hardware resources. We present an FPGA-based neural networks accelerator and its optimization framework, which can achieve optimal efficiency for various CNN models and FPGA resources. Targeting high throughput, we adopt layer-wise pipeline architecture for higher DSP utilization. To get the optimal performance, a flexible algorithm to allocate balanced hardware resources to each layer is also proposed, supported by activation buffer design. Through our well-balanced implementation of four CNN models on ZC706, the DSP utilization and efficiency are over 90%. For VGG16 on ZC706, the proposed accelerator achieves the performance of 2.58x, 1.53x and 1.35x better than the referenced non-pipeline architecture [1], pipeline architecture [2] and [3], respectively.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA11451459
• 書誌情報: 研究報告システムとLSIの設計技術（SLDM）; 巻 2021-SLDM-196, 号 29, p. 1-6, 発行日 2021-11-24
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 2188-8639
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会