A Unified Procedure to Overcome the Byzantine General's Problem for Inter-gate and Intra-gate Bridging Faults in CMOS Circuits

• Item type: Journal(1)
• 公開日: 2000-04-15
• タイトル: A Unified Procedure to Overcome the Byzantine General's Problem for Inter-gate and Intra-gate Bridging Faults in CMOS Circuits
• タイトル / 言語: en
• タイトル: A Unified Procedure to Overcome the Byzantine General's Problem for Inter-gate and Intra-gate Bridging Faults in CMOS Circuits
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: 特集：電子システムの設計技術と設計自動化
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• その他タイトル / その他のタイトル: 故障シミュレーションとテスト
• 著者所属: Graduate school of Engineering Osaka University
• 著者所属: Graduate school of Engineering Tokyo Metropolitan University
• 著者所属: Graduate school of Engineering Osaka University
• 著者所属(英): en
• 著者所属(英): Graduate school of Engineering, Osaka University
• 著者所属(英): en
• 著者所属(英): Graduate school of Engineering, Tokyo Metropolitan University
• 著者所属(英): en
• 著者所属(英): Graduate school of Engineering, Osaka University
• 著者名: Arabi, Keshk; Yukiya, Miura; Kozo, Kinoshita
• 著者名(英): Arabi, Keshk; Yukiya, Miura; Kozo, Kinoshita
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: In this paper we present two algorithms which can be used to overcome the Byzantine General's problem for bridging faults during the fault simulation and test pattern generation. The first algorithm applies to hard short bridging faults and the other applies to resistive bridging faults. These algorithms apply to inter-gate and intra-gate bridging fault. By using these propose algorithms the usual comparison between the intermediate potential and the logic threshold of the driven gates is replaced by the comparison between the equivalent resistance of the pull-up and pull-down conducting transistors. Moreover the algorithm is much faster since no spice simulation is required. The accuracy is of $?pm 0.01$? V to compare with SPICE simulation for hard short bridging fault and $?pm 0.2$? V for resistive bridging fault in the interval of intermediate voltage.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: In this paper, we present two algorithms, which can be used to overcome the Byzantine General's problem for bridging faults during the fault simulation and test pattern generation. The first algorithm applies to hard short bridging faults, and the other applies to resistive bridging faults. These algorithms apply to inter-gate and intra-gate bridging fault. By using these propose algorithms, the usual comparison between the intermediate potential and the logic threshold of the driven gates is replaced by the comparison between the equivalent resistance of the pull-up and pull-down conducting transistors. Moreover, the algorithm is much faster since no spice simulation is required. The accuracy is of $\pm 0.01$\,V to compare with SPICE simulation for hard short bridging fault and $\pm 0.2$\,V for resistive bridging fault in the interval of intermediate voltage.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN00116647
• 書誌情報: 情報処理学会論文誌; 巻 41, 号 4, p. 935-943, 発行日 2000-04-15
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-7764