An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating

• Item type: Trans(1)
• 公開日: 2014-08-04
• タイトル: An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating
• タイトル / 言語: en
• タイトル: An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: [Architectural Design] regular expression matching, partial reconfiguration, FPGA, systolic algorithm
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Graduate School of Information Sciences, Hiroshima City University
• 著者所属: Graduate School of Information Sciences, Hiroshima City University
• 著者所属: Graduate School of Information Sciences, Hiroshima City University
• 著者所属: Graduate School of Information Sciences, Hiroshima City University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Sciences, Hiroshima City University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Sciences, Hiroshima City University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Sciences, Hiroshima City University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Sciences, Hiroshima City University
• 著者名: Yoichi, Wakaba; Shin'ichi, Wakabayashi; Shinobu, Nagayama; Masato, Inagi
• 著者名(英): Yoichi, Wakaba; Shin'ichi, Wakabayashi; Shinobu, Nagayama; Masato, Inagi
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: This paper proposes a method using partial reconfiguration to realize a compact regular expression matching engine, which can update a pattern quickly. In the proposed method, a set of partial circuits, each of which handles a different class of regular expressions, are provided in advance. When a regular expression pattern is given, a compact matching engine dedicated to the pattern is implemented on FPGA by combining the partial circuits according to the given pattern using partial reconfiguration. The method can update a pattern quickly, since it does not need re-design of a circuit. Experimental results show that the proposed method reduces 60% circuit size compared with the previous method without increasing the pattern updating time significantly.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: This paper proposes a method using partial reconfiguration to realize a compact regular expression matching engine, which can update a pattern quickly. In the proposed method, a set of partial circuits, each of which handles a different class of regular expressions, are provided in advance. When a regular expression pattern is given, a compact matching engine dedicated to the pattern is implemented on FPGA by combining the partial circuits according to the given pattern using partial reconfiguration. The method can update a pattern quickly, since it does not need re-design of a circuit. Experimental results show that the proposed method reduces 60% circuit size compared with the previous method without increasing the pattern updating time significantly.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 7, p. 110-118, 発行日 2014-08-04
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会