{"created":"2025-01-18T23:47:49.878782+00:00","updated":"2025-01-21T10:45:16.243906+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00102570","sets":["934:1160:7464"]},"path":["7464"],"owner":"11","recid":"102570","title":["An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-08-04"},"_buckets":{"deposit":"343e175a-34b8-48bf-805b-333bbb1921db"},"_deposit":{"id":"102570","pid":{"type":"depid","value":"102570","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating"},{"subitem_title":"An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"[Architectural Design] regular expression matching, partial reconfiguration, FPGA, systolic algorithm","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2014-08-04","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Sciences, Hiroshima City University"},{"subitem_text_value":"Graduate School of Information Sciences, Hiroshima City University"},{"subitem_text_value":"Graduate School of Information Sciences, Hiroshima City University"},{"subitem_text_value":"Graduate School of Information Sciences, Hiroshima City University"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Sciences, Hiroshima City University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Sciences, Hiroshima City University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Sciences, Hiroshima City University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Sciences, Hiroshima City University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/102570/files/IPSJ-TSLDM0700013.pdf"},"date":[{"dateType":"Available","dateValue":"2014-08-04"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0700013.pdf","filesize":[{"value":"1.6 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"3b90b9e8-b971-4a99-8eb2-7d957ec4ea16","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yoichi, Wakaba"},{"creatorName":"Shin'ichi, Wakabayashi"},{"creatorName":"Shinobu, Nagayama"},{"creatorName":"Masato, Inagi"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yoichi, Wakaba","creatorNameLang":"en"},{"creatorName":"Shin'ichi, Wakabayashi","creatorNameLang":"en"},{"creatorName":"Shinobu, Nagayama","creatorNameLang":"en"},{"creatorName":"Masato, Inagi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12394951","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6687","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"This paper proposes a method using partial reconfiguration to realize a compact regular expression matching engine, which can update a pattern quickly. In the proposed method, a set of partial circuits, each of which handles a different class of regular expressions, are provided in advance. When a regular expression pattern is given, a compact matching engine dedicated to the pattern is implemented on FPGA by combining the partial circuits according to the given pattern using partial reconfiguration. The method can update a pattern quickly, since it does not need re-design of a circuit. Experimental results show that the proposed method reduces 60% circuit size compared with the previous method without increasing the pattern updating time significantly.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper proposes a method using partial reconfiguration to realize a compact regular expression matching engine, which can update a pattern quickly. In the proposed method, a set of partial circuits, each of which handles a different class of regular expressions, are provided in advance. When a regular expression pattern is given, a compact matching engine dedicated to the pattern is implemented on FPGA by combining the partial circuits according to the given pattern using partial reconfiguration. The method can update a pattern quickly, since it does not need re-design of a circuit. Experimental results show that the proposed method reduces 60% circuit size compared with the previous method without increasing the pattern updating time significantly.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"118","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology （TSLDM）"}],"bibliographicPageStart":"110","bibliographicIssueDates":{"bibliographicIssueDate":"2014-08-04","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"7"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":102570,"links":{}}